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Details, datasheet, quote on part number:NT128D64SH4B0GA-6K
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Datasheet text preview:
NT128D64SH4B0GA 128MB : 16M x 64 PC2700 / PC2100 Unbuffered DDR MicroDIMM 172-pin Unbuffered DDR MicroDIMM Based on DDR333/266 16Mx16 SDRAM Features
· 172-pin Micro Dual In-Line Memory Module (MicroDIMM) · 16Mx64 Double Unbuffered DDR MicroDIMM based on 16Mx16 DDR SDRAM. · Performance: PC2700 PC2100 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency -6K 2.5 166 6 333 -75B 2.5 133 7.5 266 MHz ns MHz Unit · DRAM DLL aligns DQ and DQS transitions with clock transitions. · Address and control signals are fully synchronous to positive clock edge · Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write · Auto Refresh (CBR) and Self Refresh Modes · Automatic and controlled precharge commands · 13/9/1 Addressing (row/column/bank) · 7.8 µs Max. Average Periodic Refresh Interval · Serial Presence Detect · Gold contacts · SDRAMs in 66-pin TSOP Type II Package
· Intended for 133 MHz and 166 MHz applications · Inputs and outputs are SSTL-2 compatible · VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2 · SDRAMs have 4 internal banks for concurrent operation · Module has two physical banks · Differential clock inputs · Data is read or written on both clock edges
Description
NT128D64SH4B0GA is an unbuffered 172-pin Double Data Rate (DDR) Synchronous DRAM Micro Dual In-Line Memory Module (MicroDIMM), organized as a one-bank 16Mx64 high-speed memory array. The module uses four 16Mx16 DDR SDRAMs in 400 mil TSOP-II packages. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 45.5mm long space-saving footprint. The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number NT128D64SH4B0GA-6K Speed 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL = 2) 133MHz (7.5ns @ CL = 2.5) 100MHz (10ns @ CL = 2) DDR333 PC2700 16Mx64 DDR266B PC2100 Gold 2.5V Organization Leads Power
NT128D64SH4B0GA-75B
REV 1.0
06/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B0GA 128MB : 16M x 64 PC2700 / PC2100 Unbuffered DDR MicroDIMM Pin Description
CK0, CK1, CK0, CK1 CKE0 RAS CAS WE S0 A10/AP BA0, BA1 VREF VDDID Differential Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Input/Autoprecharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag (Not used when VDD=VDDQ) DQ0-DQ63 DQS0-DQS7 DM0-DM7 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Bi-directional data strobes Input Data Mask Power (2.5V) Supply voltage for DQs (2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply (2.5V)
A0-A9, A11, A12 Address Inputs
Pinout
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Front VREF VSS DQ0 DQ1 V DD DQS0 DQ2 VSS DQ3 DQ8 V DD DQ9 DQS1 VSS DQ10 DQ11 V DD CK0 CK0 VSS DQ16 DQ17 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 Back VREF VSS DQ4 DQ5 V DD DM0 DQ6 VSS DQ7 DQ12 V DD DQ13 DM1 VSS DQ14 DQ15 V DD V DD VSS VSS DQ20 DQ21 Pin 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 Front V DD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 V DD NC A12 A9 A7 VSS A5 A3 A1 A10/AP Pin 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 B ack V DD DM2 DQ22 VSS DQ23 DQ28 V DD DQ29 DM3 VSS DQ30 DQ31 V DD CKE0 A11 A8 A6 VSS A4 A2 A0 BA1 Pin 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 Front V DD BA0 WE S0 A13 VSS DQ32 DQ33 V DD DQS4 DQ34 VSS DQ35 DQ40 V DD DQ41 DQS5 VSS DQ42 DQ43 V DD V DD Pin 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 B ack V DD RAS CAS NC RFU VSS DQ36 DQ37 V DD DM4 DQ38 VSS DQ39 DQ44 V DD DQ45 DM5 VSS DQ46 DQ47 V DD CK1 P in 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 Front VSS VSS DQ48 DQ49 V DD DQS6 DQ50 VSS DQ51 DQ56 VD D DQ57 DQS7 VSS DQ58 DQ59 V DD SDA SCL V DD S P D Pin 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 B ack CK1 VSS DQ52 DQ53 V DD DM6 DQ54 VSS DQ55 DQ60 V DD DQ61 DM7 VSS DQ62 DQ63 V DD SA0 SA1 SA2
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.0
06/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B0GA 128MB : 16M x 64 PC2700 / PC2100 Unbuffered DDR MicroDIMM Input/Output Functional Description
Symbol CK0, CK1 CK0, CK1 CKE0 Type (SSTL) (SSTL) (SSTL) Polarity Function Positive The positive line of the differential pair of system clock inputs. All the DDR SDRAM Edge address and control inputs are sampled on the rising edge of their associated clocks. Negative The negative line of the differential pair of system clock inputs. Edge Active High Active Low Active Low Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Supply Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply.
S0 RAS, CAS, WE VREF VDDQ BA0, BA1
(SSTL) (SSTL) Supply Supply (SSTL)
A0 - A9 A10/AP A11, A12
(SSTL)
-
DQ0 - DQ63 DQS0 - DQS7
(SSTL) (SSTL)
Active High Active High
DM0 - DM7 VDD, VSS SA0 - SA2 SDA SCL V DDSPD
Input Supply
REV 1.0
06/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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