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Details, datasheet, quote on part number:NT128D64SH4B1G-6K
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Datasheet text preview:
NT128D64SH4B1G NT128D64SH4B1GY 128MB : 16M x 64 PC2700 / PC2100 Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR333/266 16Mx16 SDRAM Features
· 16Mx64 Unbuffered DDR DIMM based on 16Mx16 DDR SDRAM · JEDEC Standard 184-pin Dual In-Line Memory Module · Performance: PC2700 PC2100 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency -6K 2.5 166 6 333 -75B 2.5 133 7.5 266 MHz ns MHz Unit · DRAM DLL aligns DQ and DQS transitions with clock transitions · Address and control signals are fully synchronous to positive clock edge · Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write · Auto Refresh (CBR) and Self Refresh Modes · Automatic and controlled precharge commands · 13/9/1 Addressing (row/column/bank) · 7.8 µs Max. Average Periodic Refresh Interval · Serial Presence Detect · Gold contacts · SDRAMs in 66-pin TSOP Type II Package · Lead-free and Halogen-free product available
· Intended for 133 MHz and 166 MHz applications · Inputs and outputs are SSTL-2 compatible · VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2 · SDRAMs have 4 internal banks for concurrent operation · Differential clock inputs · Data is read or written on both clock edges
Description
NT128D64SH4B1G and NT128D64SH4B1GY are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Modules (DIMM), organized as a one-bank 16Mx64 high-speed memory array. The module uses four 16Mx16 DDR SDRAMs in 400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number NT128D64SH4B1G-6K Speed 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL = 2) 133MHz (7.5ns @ CL = 2.5) 100MHz (10ns @ CL = 2) 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL = 2) 133MHz (7.5ns @ CL = 2.5) 100MHz (10ns @ CL = 2) DDR333 PC2700 16Mx64 DDR266B PC2100 Gold 2.5V Organization Leads Power
NT128D64SH4B1G-75B
NT128D64SH4B1GY-6K*
DDR333
PC2700 16Mx64 Gold 2.5V
NT128D64SH4B1GY-75B*
DDR266B
PC2100
* Lead-free and Halogen-free product
REV 1.1
06/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B1G NT128D64SH4B1GY 128MB : 16M x 64 PC2700 / PC2100 Unbuffered DDR DIMM Pin Description
CK1, CK2, CK1, CK2 CKE0 RAS CAS WE S0 A10/AP BA0, BA1 VREF VDDID Differential Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Input/Autoprecharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag (Not used when VDD=VDDQ) DQ0-DQ63 DQS0-DQS7 DM0-DM7 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Bi-directional data strobes Input Data Mask Power (2.5V) Supply voltage for DQs (2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply (2.5V)
A0-A9, A11, A12 Address Inputs
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 NC VDDQ NC DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 145 146 147 148 149 150 151 152 153 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD NC A0 NC VSS NC BA1 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 B ack VSS A6 DQ28 DQ29 V DDQ DM3 A3 DQ30 VSS DQ31 NC NC V DDQ NC NC VSS NC A10 NC V DDQ NC KEY VSS DQ36 DQ37 V DD DM4 DQ38 DQ39 VSS DQ44 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ S0 NC DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.1
06/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B1G NT128D64SH4B1GY 128MB : 16M x 64 PC2700 / PC2100 Unbuffered DDR DIMM Input/Output Functional Description
Symbol CK1, CK2 CK1, CK2 CKE0 Type (SSTL) (SSTL) (SSTL) Polarity Function Positive The positive line of the differential pair of system clock inputs. All the DDR SDRAM Edge address and control inputs are sampled on the rising edge of their associated clocks. Negative The negative line of the differential pair of system clock inputs. Edge Active High Active Low Active Low Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Supply Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply.
S0 RAS, CAS, WE VREF VDDQ BA0, BA1
(SSTL) (SSTL) Supply Supply (SSTL)
A0 - A9 A10/AP A11, A12
(SSTL)
-
DQ0 - DQ63 DQS0 - DQS7
(SSTL) (SSTL)
Active High Active High
DM0 - DM7 VDD, VSS SA0 - SA2 SDA SCL V DDSPD
Input Supply
REV 1.1
06/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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