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Details, datasheet, quote on part number:NT128S64VH4A2GM-75B
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Datasheet text preview:
NT128S64VH4A2GM 128MB : 16M x 64 SDRAM SODIMM
16Mx64 bit One Bank Small Outline SDRAM Module based on 16Mx16, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
Features
! 144 Pin JEDEC Standard, 8 Byte Small Outline Dual-In-line Memory Module ! ! ! ! ! ! ! ! ! ! 16Mx64 Synchronous DRAM SO DIMM Inputs and outputs are LVTTL (3.3V) compatible 10 Ohm Resistors on DQs Single 3.3V ± 0.3V Power Supply Single Pulsed RAS interface ! ! ! ! ! !
Programmable Operation: - CAS Latency: 2, 3 - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8, - Operation: Burst Read and Write or Multiple Burst Read with Single Write Suspend Mode and Power Down Mode 13/9/2 Addressing (Row/Column/Bank) 8192 refresh cycles distributed across 64ms Serial Presence Detect Gold contacts
SDRAMs have four internal banks Fully Synchronous to positive Clock Edge Data Mask for Byte Read/Write control Auto Refresh (CBR) and Self Refresh Automatic and controlled Precharge Commands
Description
NT128S64VH4A2GM is a 144-pin Synchronous DRAM Small Outline Dual In-line Memory Module (SO DIMM) that is organized as a 16Mx64 high-speed memory array. The SO DIMM uses four 16Mx16 SDRAMs in 400mil TSOP II packages and achieves high-speed data transfer rates of up to 133 MHz by employing a prefetch / pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power. All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are sampled at the positive edge of the externally supplied clock (CK0). Internal operating modes are defined by combinations of the RAS , CAS , WE , S0 , DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 15 bit address bus accepts address information in a row/column multiplexing arrangement.
Prior to any access operation, the CAS latency, burst type, burst length, and burst operation type must be programmed into the SO DIMM by address inputs A0-A9 during the mode register set cycle. The SO DIMM uses serial presence detects implemented via a serial EEPROM using the two pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the customer. All Nanya 144-pin SO DIMMs provide a high performance, flexible 8-byte interface in a 2.66" long space-saving footprint.
Ordering Information
Part Number Speed MHz. 143MHz 133MHz 133MHz 100MHz 125MHz 100MHz CL 3 2 3 2 3 2 t RCD 3 2 3 2 3 2 t RP 3 2 3 2 3 2 16Mx64 Gold 3.3V Organization Leads Power
NT128S64VH4A2GM-7K
NT128S64VH4A2GM-75B
NT128S64VH4A2GM-8B * CL = CAS Latency
REV 1.0
02/2002
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128S64VH4A2GM 128MB : 16M x 64 SDRAM SODIMM Pin Description
CK0 CKE0 RAS CAS WE S0 A0-A9, A11, A12 A10 / AP BA0, BA1 Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address DQ0-DQ63 DQMB0-DQMB7 VDD VSS NC SCL SDA DU Data input/output Data Mask Power (3.3V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Don't use
Pinout
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 CK0 VDD RAS WE S0 NC DU VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 CKE0 VDD CAS NC A12 NC NC VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 Voltage Key Pin 51 53 55 57 59 Front DQ14 DQ15 VSS NC NC Pin 52 54 56 58 60 Back DQ46 DQ47 VSS NC NC Pin 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/ AP VDD DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS SCL VDD
Note: All pin assignments are consistent for all 8-byte versions.
REV 1.0
02/2002
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128S64VH4A2GM 128MB : 16M x 64 SDRAM SODIMM SDRAM DIMM Block Diagram (1 Bank, 16Mx16 SDRAMs)
S0 DQMB0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ1 0 DQ1 1 DQ1 2 DQ1 3 DQ1 4 DQ1 5 DQ8 DQ9 DQ1 0 DQ1 1 DQ1 2 DQ1 3 DQ1 4 DQ1 5 CS
DQMB4
DQ3 2 DQ3 3 DQ3 4 DQ3 5 DQ3 6 DQ3 7 DQ3 8
LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UD QM DQ4 0 DQ4 1 DQ4 2 DQ4 3 DQ4 4 DQ4 5 DQ4 6 DQ4 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS
D0 DQMB5
DQ3 9
D2
DQMB1
DQMB2
DQ1 6 DQ1 7 DQ1 8 DQ1 9 DQ2 0 DQ2 1 DQ2 2 DQ2 3
LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ2 4 DQ2 5 DQ2 6 DQ2 7 DQ2 8 DQ2 9 DQ3 0 DQ3 1 DQ8 DQ9 DQ1 0 DQ1 1 DQ1 2 DQ1 3 DQ1 4 DQ1 5
CS
DQMB6
DQ4 8 DQ4 9 DQ5 0 DQ5 1 DQ5 2 DQ5 3 DQ5 4
LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UD QM DQ5 6 DQ5 7 DQ5 8 DQ5 9 DQ6 0 DQ6 1 DQ6 2 DQ6 3 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS
D1 DQMB7
DQ5 5
D3
DQMB3
RAS CAS CKE0 WE A0-A12 BA0 BA1 DQn
SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 SDRAMs D0-D3 Every DQ pin of SDRAM
SCL A0
SPD A1 A2 SDA CK0
D0 D1 D2 D3 10 ohm
VDD VSS
D0 - D3 D0 - D3
CK1 10p F
REV 1.0
02/2002
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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