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Details, datasheet, quote on part number:NT1GD64S8HA0FM-6K
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Datasheet text preview:
NT1GD64S8HA0FM 1GB : 128M x 64 PC2700 / PC2100 Unbuffered DDR SO-DIMM 200-pin Unbuffered DDR SO-DIMM Based on DDR333/266 64Mx8 SDRAM Features
· 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) · 128Mx64 Double Unbuffered DDR SO-DIMM based on 64Mx8 DDR SDRAM. · Performance: PC2700 PC2100 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency -6K 2.5 166 6 333 -75B 2.5 133 7.5 266 MHz ns MHz Unit · DRAM DLL aligns DQ and DQS transitions with clock transitions. · Address and control signals are fully synchronous to positive clock edge · Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write · Auto Refresh (CBR) and Self Refresh Modes · Automatic and controlled precharge commands · 13/11/2 Addressing (row/column/bank) · 7.8 µs Max. Average Periodic Refresh Interval · Serial Presence Detect · Gold contacts · SDRAMs in 60-ball FBGA Package
· Intended for 133 MHz and 166 MHz applications · Inputs and outputs are SSTL-2 compatible · VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2 · SDRAMs have 4 internal banks for concurrent operation · Module has two physical banks · Differential clock inputs · Data is read or written on both clock edges
Description
NT1GD64S8HA0FM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as a two-bank 128Mx64 high-speed memory array. The module uses sixteen 64Mx8 DDR SDRAMs in 60-ball FBGA packages. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number NT1GD64S8HA0FM-6K Speed 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL = 2) 133MHz (7.5ns @ CL = 2.5) 100MHz (10ns @ CL = 2) DDR333 PC2700 128Mx64 DDR266B PC2100 Gold 2.5V Organization Leads Power
NT1GD64S8HA0FM-75B
REV 0.2 (Preliminary)
05/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GD64S8HA0FM 1GB : 128M x 64 PC2700 / PC2100 Unbuffered DDR SO-DIMM Pin Description
CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 RAS CAS WE S0, S1 A0-A9, A11, A12 A10/AP BA0, BA1 VREF VDDID Differential Clock Inputs. Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag. DQ0-DQ63 DQS0-DQS7, DQS9-DQS16 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Bidirectional data strobes Power (2.5V) Supply voltage for DQs (2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply (2.5V)
Pinout
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS DQS8 NC VDD NC DU VSS CK2 CK2 VDD CKE1 DU A12 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 B ack VSS DQ23 DQ28 V DD DQ29 DM3 VSS DQ30 DQ31 V DD NC NC VSS NC NC V DD NC DU VSS VSS V DD V DD CKE0 DU A11 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Front A9 VSS A7 A5 A3 A1 V DD A10/AP VDD WE S0 DU VSS DQ32 DQ33 V DD DQS4 DQ34 VSS DQ35 DQ40 V DD DQ41 DQS5 VSS Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 B ack A8 VSS A6 A4 A2 A0 V DD BA1 RAS CAS S1 DU VSS DQ36 DQ37 V DD DM4 DQ38 VSS DQ39 DQ44 V DD DQ45 DM5 VSS P in 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 B ack DQ46 DQ47 V DD CK1 CK1 VSS DQ52 DQ53 V DD DM6 DQ54 VSS DQ55 DQ60 V DD DQ61 DM7 VSS DQ62 DQ63 V DD SA0 SA1 SA2 DU
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 0.2 (Preliminary)
05/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GD64S8HA0FM 1GB : 128M x 64 PC2700 / PC2100 Unbuffered DDR SO-DIMM Input/Output Functional Description
Symbol CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 Type (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the S0, S1 (SSTL) Active Low Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. RAS, CAS, WE VREF VDDQ BA0, BA1 (SSTL) Supply Supply (SSTL) When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11, A12 when sampled at the rising clock edge. In addition to the column address, AP is used to (SSTL) invoke autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 DQS0 - DQS7, DQS9 DQS16 VDD, VSS SA0 SA2 SDA SCL VDDSPD Supply (SSTL) (SSTL) Supply Active High Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply.
(SSTL)
REV 0.2 (Preliminary)
05/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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