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Details, datasheet, quote on part number:NT256D64S88A0G-8B
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Datasheet text preview:
NT256D64S88A0G 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DIMM 184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 32Mx8 SDRAM Features
· 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module · 32Mx64 Double Data Rate (DDR) SDRAM DIMM · Performance : PC1600 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency - 8B 2 100 10 200 PC2100 - 75B 2.5 133 7.5 266 - 7K 2 133 7.5 266 MHz ns MHz Unit · DRAM DLL aligns DQ and DQS transitions with clock transitions. Also aligns QFC transitions with clock during Read cycles · Address and control signals are fully synchronous to positive clock edge · Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write · Auto Refresh (CBR) and Self Refresh Modes · Automatic and controlled precharge commands · 13/10/2 Addressing (row/column/bank) · 7.8 µs Max. Average Periodic Refresh Interval · Serial Presence Detect · Gold contacts · SDRAMs in 66-pin TSOP Type II Package
· Intended for 100 MHz and 133 MHz applications · Inputs and outputs are SSTL-2 compatible · VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2 · Single Pulsed RAS interface · SDRAMs have 4 internal banks for concurrent operation · Module has one physical bank · Differential clock inputs · Data is read or written on both clock edges
Description
NT256D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all devices on the DIMM. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The last 128 bytes are available to the customer. All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.
Ordering Information
Part Number NT256D64S88A0G-7K Speed 143MHz (7ns @ CL = 2.5 ) 133MHz (7.5ns @ CL= 2 ) 133MHz (7.5ns @ CL= 2.5 ) 100MHz (10ns @ CL = 2 ) 125MHz (8ns @ CL = 2.5 ) 100MHz (10ns @ CL = 2 ) PC2100 Organization Leads Power
NT256D64S88A0G 75B
PC2100
32Mx64
Gold
2.5V
NT256D64S88A0G 8B
PC1600
Preliminary 08 / 2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D64S88A0G 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DIMM Pin Description
CK0, CK1, CK2
CK0 , CK1 , CK2
CKE0
Differential Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag.
DQ0-DQ63 DQS0-DQS7, DQS9-DQS16 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD
Data input/output Bidirectional data strobes Power (2.5V) Supply voltage for DQs(2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply(2.5V)
RAS CAS
WE
S0
A0-A9, A11,A12 A10/AP BA0, BA1 VREF VDDID
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 NC VDDQ NC DQ20 A12 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD NC A0 NC VSS NC BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 145 146 147 148 149 150 151 152 153 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Back VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 NC NC VDDQ CK0 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back
RAS
DQ45 VDDQ
WE
DQ41
CAS
VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS
S0
NC DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
CK2
CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
CK0
VSS NC A10 NC VDDQ NC KEY VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44
CK1
VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
Preliminary 08 / 2001
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D64S88A0G 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DIMM Input/Output Functional Description
Symbol CK0 , CK1, CK2 Type (SSTL) Polarity Positive Edge Function The positive line of the differential pair of system clock inputs which drives the input to the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising edge of their associated clocks. on-DIMM PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS , CAS , W E define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11,A12 when sampled at the rising clock edge. In addition to the column address, AP is used to (SSTL) invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63, DQS0 - DQS7 DQS9 - DQS16 VDD , VSS SA0 SA2 SDA SCL V DDSPD Supply (SSTL) (SSTL) Supply Active High Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply.
CK0 , CK1 , CK2
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to the Edge Active High Active Low Active Low
CKE0
(SSTL)
S0
(SSTL)
RAS , CAS , W E
VREF VDDQ BA0, BA1
(SSTL) Supply Supply (SSTL)
Preliminary 08 / 2001
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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