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Details, datasheet, quote on part number:NT5SV8M16CT-8B
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Datasheet text preview:
NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT
128Mb Synchronous DRAM Features
· High Performance:
-7K 3 CL=2 fC K tC K tA C tA C Clock Frequency C l o c k Cycle C l o c k Access T i m e1 C l o c k Access T i m e2 133 7.5 -- 5.4 -75B, CL=3 133 7.5 -- 5.4 -8B, CL=2 100 10 -- 6 Units MHz ns ns ns
1 . T e r m i n a t e d load. See AC Characteristics on page 37. 2 . U n t e r m i n a t e d load. See AC Characteristics on page 37. 3 . tR P = tR C D = 2 CKs
· Single Pulsed RAS Interface · Fully Synchronous to Positive Clock Edge · Four Banks controlled by BS0/BS1 (Bank Select)
· · · · · · · · · · · · · · ·
Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 4096 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V ± 0.3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II
Description
The NT5SV32M4CT, NT5SV16M8CT, and NT5SV8M16CT are four-bank Synchronous DRAMs organized as 8Mbit x 4 I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and 2Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC's advanced 128Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS , CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (BS0, BS1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A11, BS0, BS1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported.
REV 1.0
M a y , 2001
1
© NANYA TECHNOLOGY CORP. All rights reserved.
N A N Y A TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT
128Mb Synchronous DRAM Pin Assignments for Planar Components (Top View)
VD D DQ0 V DDQ DQ1 DQ2 VSSQ DQ3 DQ4 V DDQ DQ5 DQ6 VSSQ DQ7 VD D LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 V DD V DD DQ0 V DDQ NC DQ1 V SSQ NC DQ2 V DDQ NC DQ3 VSSQ NC V DD NC WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 V DD V DD NC VDDQ NC DQ0 VS S Q NC NC VDDQ NC DQ1 VS S Q NC V DD NC WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS NC VSSQ NC DQ3 V DDQ NC NC VSSQ NC DQ2 V DDQ NC V SS NC DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 V SS V SS DQ7 V SSQ NC DQ6 V DDQ NC DQ5 V SSQ NC DQ4 V DDQ NC V SS NC DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 V SS VS S DQ15 VS S Q DQ14 DQ13 V DDQ DQ12 DQ11 VS S Q DQ10 DQ9 V DDQ DQ8 VS S NC UDQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VS S
54-pin Plastic TSOP(II) 400 mil 8Mbit x 4 I/O x 4 Bank NT5SV32M4CT 4Mbit x 8 I/O x 4 Bank NT5SV16M8CT 2Mbit x 16 I/O x 4 Bank NT5SV8M16CT
REV 1.0
M a y , 2001
2
© NANYA TECHNOLOGY CORP. All rights reserved.
N A N Y A TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT
128Mb Synchronous DRAM Pin Description
CK CKE CS RAS CAS WE BS1, BS0 A 0 - A11 Clock Input C l o c k Enable Chip Select R o w Address Strobe C o l u m n Address Strobe Write Enable B a n k Select A d d r e s s Inputs DQ0-DQ15 D Q M , LDQM, UDQM V DD V SS V DDQ V SSQ NC -- D a t a Input/Output D a t a Mask P o w e r (+3.3V) Ground P o w e r for DQs (+3.3V) G r o u n d for DQs N o Connection --
Input/Output Functional Description
Symbol CLK CKE CS RAS, CAS, WE B S 0 , BS1 Type Input Input Input Input Input Polarity Positive Edge A c t i v e High A c t i v e Low A c t i v e Low -- Function T h e system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. A c t i v a t e s the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. C S enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. W h e n sampled at the positive rising edge of the clock, CAS , RAS , and WE define the operation to be executed by the SDRAM. S e l e c t s which bank is to be active. D u r i n g a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. D u r i n g a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9, CA11) when sampled at the rising clock edge. A 1 0 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. D a t a Input/Output pins operate in the same manner as on conventional DRAMs.
A0 - A11
Input
--
D Q 0 - DQ15
InputOutput
--
DQM LDQM UDQM
Input
T h e Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. A c t i v e High DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. -- -- P o w e r and ground for the input buffers and the core logic. I s o l a t e d power supply and ground for the output buffers to provide improved noise immunity.
V D D, VSS V D D Q VS S Q
Supply Supply
REV 1.0
M a y , 2001
3
© NANYA TECHNOLOGY CORP. All rights reserved.
N A N Y A TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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