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Details, datasheet, quote on part number:100336FC
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| Part: | 100336FC |
| Category: | Logic => Military/Aerospace->ECL |
| Description: | 100336 - Low Power 4-Stage Counter/shift Register, Package: Cerquad, Pin Nb=24 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download 100336FC datasheet File size : 327 kB |
| Request For quote: | Find where to buy 100336FC
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Datasheet text preview:
100336 Low Power 4-Stage Counter/Shift Register
August 1998
100336 Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (Sn) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP, CET) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET) input also doubles as a Serial Data (D0) input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count (TC) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The individual Preset (Pn) inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flip-flops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 k pull-down resistors.
Features
n n n n n 40% power reduction of the 100136 2000V ESD protection Pin/function compatible with 100136 Voltage compensated operating range = -4.2V to -5.7V Standard Microcircuit Drawing (SMD) 5962-9230601
Logic Symbol
Pin Names CP CEP D0/CET S0 S2 MR
DS100307-1
Description Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs
P0 P3 D3 TC Q0 Q3 Q0 Q3
© 1998 National Semiconductor Corporation
DS100307
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Connection Diagrams
24-Pin DIP 24-Pin Quad Cerpak
DS100307-3
DS100307-2
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Logic Diagram
DS100307-5
3
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Function Select Table
S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H Function Parallel Load Complement Shift Left Shift Right Count Down Clear Count Up Hold
Truth Table
Q0 = LSB Inputs MR L L L L L L L L L L L L H H H H H H H H H S2 L L L L H H H H H H H H L L L L H H H H H S1 L L H H L L L L H H H H L L H H L L L H H S0 L H L H L L L H L L L H L H L H L L H L H CEP X X X X L H X X L H X X X X X X X X X X X D0/CET X X X X L L H X L L H X X X X X L H X X X D3 X X X X X X X X X X X X X X X X X X X X X CP
N N N N N
Outputs Q3 P3 Q3 D3 Q2 Q3 Q3 L Q3 Q3 Q3 L L L L L L L L L Q2 P2 Q2 Q3 Q1 Q2 Q2 L Q2 Q2 Q2 L L L L L L L L L Q1 P1 Q1 Q2 Q0 Q1 Q1 L Q1 Q1 Q1 L L L L L L L L L Q0 P0 Q0 Q1 D0 Q0 Q0 L Q0 Q0 Q0 L L L L L L L L L TC L L D3 Q3(Note 1) 1 1 H H 2 2 H H L L L L L H H H H Asynchronous Master Reset Invert Shift to LSB Shift to MSB Count Down Count Down with CEP not active Count Down with CET not active Clear Count Up Count Up with CEP not active Count Up with CET not active Hold Mode Preset (Parallel Load)
(Q0 3) minus 1
X X
N N
(Q0 3) plus 1
X X X X X X X X X X X X
1 = L if Q0 Q3 = LLLL H if Q0 Q3 LLLL 2 = L if Q0 Q3 = HHHH H if Q0 Q3 HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care N = LOW-to-HIGH Transition Note 1: Before the clock, TC is Q3 After the clock, TC is Q2
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) -65°C to +150°C +175°C -7.0V to +0.5V VEE to +0.5V -50 mA 2000V
Recommended Operating Conditions
Case Temperature (TC) Military Supply Voltage (VEE) -55°C to +125°C -5.7V to -4.2V
Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version DC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND, T Symbol VOH Parameter Output HIGH Voltage Min -1025 -1085 VOL Output LOW Voltage
C
= -55°C to +125°C Units mV mV mV mV mV mV TC 0°C to +125°C VIN = VIH
(Max)
Max -870 -870
Conditions Loading with 50 to -2.0V
Notes
-55°C 0°C to +125°C -55°C 0°C to +125°C
or VIL (Min)
(Notes 4, 5, 6)
-1830 -1620 -1830 -1555
VOHC
Output HIGH Voltage
-1035 -1085
VIN = VIH
(Min)
Loading with 50 to -2.0V (Notes 4, 5, 6)
-55°C 0°C to +125°C -55°C -55°C to +125°C -55°C to +125°C -55°C to +125°C 0°C to +125°C -55°C -55°C to +125°C
or VIL (Max)
VOLC
Output LOW Voltage
-1610 -1555
mV mV mV mV µA
VIH VIL IIL IIH
Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current
-1165
-870
Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VEE = -4.2V VIN = VIL (Min) VEE = -5.7V VIN = VIH(Max) Inputs Open VEE = -4.2V to -4.8V VEE = -4.2V to -5.7V
(Notes 4, 5, 6, 7) (Notes 4, 5, 6, 7) (Notes 4, 5, 6)
-1830 -1475 0.50 240 340
µA µA mA
(Notes 4, 5, 6)
IEE
Power Supply Current -185 -195 -70 -70
(Notes 4, 5, 6)
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 5: Screen tested 100% on each device at -55°C, +25°C, and +125°C, Subgroups 1, 2, 3, 7, and 8. Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at -55°C, +25°C, +125°C, Subgroups A1, 2, 3, 7, and 8. Note 7: Guaranteed by applying specified input conditon and testing VOH/VOL.
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