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Part: 11C90C
Category:
Communication
-> Freq/Signal Converters/Generators
Description: 650 MHZ Prescalers (obsolete)
Company: National Semiconductor Corporation
Datasheet: Download 11C90C datasheet File size : 267 kB
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Datasheet text preview:
11C90 11C91 650 MHz Prescalers
Not Intended For New Designs
August 1992
11C90 11C91 650 MHz Prescalers
General Description
The 11C90 and 11C91 are high-speed prescalers designed specifically for communication and instrumentation applications All discussions and examples in this data sheet are T applicable to the 11C91 as well as the 11C90 b he 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6 Toth over a frequency range from DC to typically 650 MHz he division ratio is controlled by the Mode Control The divide-by-10 or -11 capability allows the use of pulse swallowing techniques to control high-speed counting modulos by lower-speed circuits The 11C90 may be used with either I ECL or TTL power supplies n addition to the ECL outputs Q and Q the 11C90 contains an ECL-to-TTL converter and a TTL output The TTL output o bperates from the same VCC and VEE levels as the counter ut a separate pin is used for the TTL circuit VEE This minimizes noise coupling when the TTL output switches and L also allows power consumption to be reduced by leaving th T e separate VEE pin open if the TTL output is not used o facilitate capacitive coupling of the clock signal a 400X resistor (VREF) is connected internally to the VBB reference C onnecting this resistor to the Clock Pulse input (CP) autoM matically centers the input about the switching threshold aximum frequency operation is achieved with a 50% duty E cycle ach of the Mode Control inputs is connected to an internal 2 kX resistor with the other end uncommitted (RM1 and RM2) An M input can be driven from a TTL circuit operating from the same VCC by connecting the free end of the associated 2 kX resistor to VCCA When an M input is driven from the ECL circuit the 2 kX resistor can be left open or if required can be connected to VEE to act as a pull-down resistor
ogic Symbol
Connection Diagram
16-Pin DIP
TL F 9892 2
TL F 9892 1
Pin Names CE CP Mn MS QQ QTTL RMn VREF
Description Count Enable Input (Active LOW) Clock Pulse Input Count Modulus Control Input Asynchronous Master Set Input ECL Outputs TTL Output 2 kX Resistor to Mn 400X Resistor to VBB
C1995 National Semiconductor Corporation
TL F 9892
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
Above which the useful life may be impaired p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Maximum Junction Temperature (TJ) Supply Voltage Range Input Voltage (DC) Output Current (DC Output HIGH) Operating Range Lead Temperature (Soldering 10 sec )
b 65
Recommended Operating Conditions
Min Ambient Temperature (TA) Commercial Military Supply Voltage (VEE) Commercial Military 0C
b 55
Typ
Max
a 75 C a 125 C
C to a 150 C a 150 C
VEE to GND b 50 mA
C
b 5 2V b 5 2V
b 7 0V to GND
b 5 7V b 5 7V
b 4 7V b 4 7V
b 5 7V to b 4 7V
300 C
TTL Input Output Operation DC Electrical Characteristics
Over Operating Temperature and Voltage Range unless otherwise noted Pins 12 and 13 e GND Symbol VIH VIL VOH VOL IIL ISC Parameter Input HIGH Voltage M1 and M2 Inputs Input LOW Voltage M1 and M2 Inputs Q Output HIGH Voltage TTL Output Qutput LOW Voltage O TTL Output Mput LOW Current In 1 and M2 Inputs C utput Short Circuit O urrent
b 20
Min
Typ (Note 3) 41 33
Max
Units V V V
Conditions Guaranteed Input HIGH Threshold Voltage (Note 4) VCC e VCCA e 5 0V Guaranteed Input LOW Threshold Voltage (Note 4) VCC e VCCA e 5 0V VCC e VCCA e Min IOH e b640 mA VCC e VCCA e Min IOL e 20 0 mA VCC e VCCA e Max VIN e 0 4V Pins 6 7 e VCC VCC e VCCA e Max VOUT e 0 0V Pin 14 e VCC
23
33 02
b2 3 b 35
05
b5 0 b 80
V mA mA
AC Electrical Characteristics
VCC e VCCA e 5 0V Nominal VEE e GND TA e a 25 C Symbol tPLH tPHL tPLH ts th tTLH tTHL fMAX Parameter Propagation Delay (50% to 50%) CP to QTTL Propagation Delay (50% to 50%) MS to QTTL Mode Control Setup Time Mode Control Hold Time Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Count Frequency 550 600 4 0 Min 6 Typ 10 12 2
b2
Max 14 17
Units ns ns ns ns ns ns MHz
Conditions See Figure 1
10 2 650 650
b 55 C to a 125 C 0 C to a 75 C Clock Input AC Coupled 350 mV Peak-to-Peak Sinewave (Note 5)
2
ECL Operation
Commercial Version
DC Electrical Characteristics
VCC e VCCA e GND VEE e b5 2V Symbol VOH Parameter Output HIGH Voltage Q and Q Output LOW Voltage Q and Q Input HIGH Voltage Min
b 1060 b 1025 b 980 b 1820 b 1135 b 1095 b 1035 b 1870 b 1850 b 1830
Typ
b 995 b 960 b 910 b 1705
Max
b 905 b 880 b 805 b 1620 b 840 b 810 b 720 b 1500 b 1485 b 1460
Units mV
TA 0C
a 25 a 75 a 75
Conditions Load e 50X to b2V
C C C
Guaranteed Input HIGH Signal (Note 6) Guaranteed Input LOW Signal VIN e VIHA
VOL VIH
mV
0 C to 0C a 25 C a 75 C 0C
a 25 a 75 a 25 a 25 a 25 a 25 a 75 a 75 a 25
mV
VIL
Input LOW Voltage
mV
C C C C C C C C C
IIH
Input HIGH Current CP Input (Note 1) MS Input M1 and M2 Input Input LOW Current Power Supply Current Operating Supply Voltage Range Reference Voltage 05
b 110 b 119 b5 7 b 1550 b 75 b5 2
400 400 250
mA mA mA
IIL IEE VEE VREF
VIN e VILB Pins 6 7 13 not connected
0 C to 0 C to
b4 7 b 1150
V mV
VRM1 e VRM2 e b5 2V IN e b10 0 mA
AC Electrical Characteristics
TA e 0 C to a 75 C VCC e VCCA e GND VEE e b5 2V Symbol tPLH
PHL
Parameter Propagation Delay (50% to 50%) CP to Q Propagation Delay ( 50% to 50%) MS to Q Setup Time M to CP Hold Time M to CP Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Maximum Clock Frequency
0C Typ 1 3 8 7
a 25
C
Max 30 60
a 75
C
Min 13
Typ 20 40
Typ 25 45 20
b2 0
Units
Conditions Output RL e 50X to b2 0V Input tri e tfi e 2 0 g 0 1 ns (20% to 80%) See Figure 1
ns ns ns ns ns ns
tPLH ts th tTLH tTHL fMAX
20
b2 0
40 00
20
b2 0
10 10
10 10
20 20
10 10
650
600
650 3
625
MHz
AC Coupled Input 350 mV Peak-to-Peak fMAX is Guaranteed to be 575 MHz Min at 0 C to a 75 C
ECL Operation Military Version DC Electrical Characteristics
VCC e VCCA e GND VEE e b5 2V Symbol VOH Parameter Output HIGH Voltage Q and Q Output LOW Voltage Q and Q Input HIGH Voltage Min
b 1100 b 980 b 910 b 1820 b 1190 b 1095 b 975 b 1890 b 1850 b 1800
Typ
b 1030 b 910 b 820 b 1705
Max
b 900 b 820 b 670 b 1620 b 905 b 810 b 690 b 1525 b 1485 b 1435
Units mV
TA
b 55 C a 25 C a 125 C b 55 C to a 125 C b 55 C a 25 C a 125 C b 55 C a 25 C a 125 C a 25 a 25 a 25 a 25 a 25
Conditions Load e 100X to b2V
VOL VIH
mV
mV
Guaranteed Input HIGH Signal (Note 6) Guaranteed Input LOW Signal VIN e VIHA
VIL
Input LOW Voltage
mV
IIH
Input HIGH Current CP Input (Note 1) MS Input M1 and M2 Input Input LOW Current Power Supply Current 05
b 110 b 75 b 119
400 400 250
mA mA mA mA
C C C C C
VIN e VILB Pins 6 7 13 not connected
IIL IEE
b 55 C to a 125 C b 55 C to a 125 C a 25
VEE VREF
Operating Supply Voltage Range Reference Voltage
b5 7 b 1550
b5 2
b4 7 b 1150
V mV
C
VRM1 e VRM2 e b5 2V IN e b10 0 mA
AC Electrical Characteristics
TA e b55 C to a 125 C VCC e VCCA e GND VEE e b5 2V Symbol tPLH
PHL
Parameter Propagation Delay (50% to 50%) CP to Q Propagation Delay (50% to 50%) MS to Q Setup Time M to CP Hold Time M to CP Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Maximum Clock Frequency
b 55
C
Min 13
a 25
C
Max 30 60
a 125
C
Typ 1 3 5 5
Typ 20 40
Typ 30 50 20
b2 0
Units
Conditions Output RL e 50X to b2 0V Input tri e tfi e 2 0 g 0 1 ns (20% to 80%) See Figure 1
ns ns ns ns ns ns
tPLH t
s
20
b2 0
40 00
20
b2 0
th tTLH tTHL fMAX
10 10
10 10
20 20
10 10
700 N
600
650
600
MHz
AC Coupled Input 350 mV Peak-to-Peak fMAX is Guaranteed to be 550 MHz Min at b55 C to a 125 C
Note 1 Conditions for testing not shown in the Table are chosen to guarantee operation under ``worst case'' conditions ote 2 The specified limits represent the ``worst case'' value for the parameter Since these ``worst case'' values normally occur at the temperature and supply N voltage extremes additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges Note 3 Typical limits are at VCC e 5 0V and TA e a 25 C ote 4 The M1 and M2 threshold specifications are normally referenced to the VCC potential as shown in the ECL operation tables Using VEE (GND) as the reference as in normal TTL practice effectively makes the threshold vary directly with VCC Threshold is typically 1 3V below VCC (e g a3 7V at VCC e a 5V) A signal swing about threshold of g 0 4V is adequate which gives the state VIH and VIL values The internal 2 kX resistors are intended to pull TTL outputs up to the N quired VIH range as discussed in the Functional Description and shown in Figure 5 re Note 5 TTL Output Signal swing is guaranteed at fMAX over temperature range ote 6 M1 or M2 can be tied to VCC for fixed divide-by-ten operation 4
TL F 9892 3
TL F 9892 4
V Conditions
CC e a 2 0V VEE e b 3 2V RT e 50X (scope input impedance) CL e Jig and stray capacitance k 5 0 pF I1 e L2 e equal 50X impedance lines C e 0 1 pF
Note 7 C Use high impedance to test QTTL onnect pin 13 to VEE N ote 8 A High frequency test use AC coupled input as in Figure 3 For djust input amplitude to 350 mV peak-to-peak F
IGURE 1 AC Test Circuit
5
Others parts begin by 11
11-1 11-2 11-3
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