54ABT646 Octal Transceivers and Registers with TRI-STATE Outputs
54ABT646 Octal Transceivers and Registers with TRI-STATE ® Outputs
The 'ABT646 consists of bus transceiver circuits with TRI-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register.
Features
n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability mA n Guaranteed multiple output switching specifications n Output switching specified for both 50 pF and 250 pF loads n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9457701
Military 54ABT646W-QML 54ABT646E-QML Package Number E28A 24-Lead Cerpack 28-Lead Ceramic Leadless Chip Carrier, Type C Package Description 24-Lead Ceramic Dual-In-Line
TRI-STATE is a registered trademark of National Semiconductor Corporation.
Pin Names A0A7 B0B7 CPAB, CPBA SAB, SBA OE DIR Select Inputs Output Enable Input Direction Control Input Data Register A Inputs/ TRI-STATE Outputs Data Register B Inputs/ TRI-STATE Outputs Clock Pulse Inputs Description
FIGURE 1. Real Time Transfer B-Bus to A-Bus
Data I/O (Note 1) Output Input Output Input Isolation
Clock An Data into A Register Clock Bn Data into B Register to Bn Real Time (Transparent Mode) Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to An Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
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