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Details, datasheet, quote on part number: 54ABT652W-QML
 
 
Part number54ABT652W-QML
CategoryInterface and Interconnect => Transceivers
TitleBus Oriented Circuits
DescriptionOctal Transceivers And Registers With Tri-state Outputs
CompanyNational Semiconductor Corporation
DatasheetDownload 54ABT652W-QML datasheet
Request For QuoteFind where to buy 54ABT652W-QML
 


 
Specifications, Features, Applications
54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs
54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs

The 'ABT652 consists of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9324201

Features

Commercial 54ABT652W-QML 54ABT652E-QML Package Number E28A 24-Lead Ceramic Dual-in-line 24-Lead Cerpack 28-Lead Ceramic Leadless Chip Carrier, Type C Package Description

TRI-STATE is a registered trademark of National Semiconductor Corporation.

Pin Names A0A7 B0B7 CPAB, CPBA SAB, SBA OEAB, OEBA Description Data Register A Inputs/TRI-STATE Outputs Data Register B Inputs/TRI-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

In the transceiver mode, data present at the HIGH impedance port may be stored in either the or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the 'ABT652C. Data on the or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.




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