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Part: 54ACT109L
Category:
Logic
-> Flip-Flops
Description: Dual JK Positive Edge-triggered Flip-flop
Company: National Semiconductor Corporation
Datasheet: Download 54ACT109L datasheet File size : 275 kB
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Datasheet text preview:
54AC109 · 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
August 1998
54AC109 · 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 'AC/'ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to 'AC/'ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
n n n n ICC reduced by 50% Outputs source/sink 24 mA 'ACT109 has TTL-compatible inputs Standard Military Drawing (SMD) -- 'AC109: 5962-89551 -- 'ACT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1 DS100267-7
Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2
DS100267-2
Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100267
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Connection Diagrams
Pin Assignment for DIP and Flatpak Pin Assignment for LCC
DS100267-3 DS100267-4
Truth Table
(each half) Inputs SD L H L H H H H H CD H L L H H H H H CP X X X
N N N N
Outputs J X X X L H L H X K X X X L L H H X H Q0 Q H L H L Toggle Q0 Q0 L Q0 Q L H H H
L
H = HIGH Voltage Level L = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q0(Q0) = Previous Q0 (Q0) before LOW-to-HIGH Transition of Clock
Logic Diagram
(one half shown)
DS100267-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
125 mV/ns
± 50 mA ± 50 mA -65°C to +150°C
175°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54AC TA = -55°C to +125°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 12 mA V µA IOL = 24 mA IOL = 24 mA VI = VCC, GND V IOUT = -50 µA V VOUT = 0.1V or VCC - 0.1V V VOUT = 0.1V or VCC - 0.1V Units Conditions
3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5
2.4 3.7 4.7 0.1 0.1 0.1 V
3.0 4.5 5.5 IIN Maximum Input Leakage Current IOLD IOHD (Note 3) Minimum Dynamic Output Current 5.5 5.5 5.5
0.5 0.5 0.5
± 1.0
50 -50
mA mA
VOLD = 1.65V Max VOHD = 3.85V Min
3
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DC Characteristics for 'AC Family Devices
Symbol ICC Parameter Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
VCC (V) 5.5
54AC TA = -55°C to +125°C Guaranteed Limits 40.0
Units µA
Conditions VIN = VCC or GND
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25°C is identical to 74AC @ 25°C.
DC Characteristics for 'ACT Family Devices
Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = -55°C to +125°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH IOH = -24 mA IOH = -24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC - 2.1V V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA Units Conditions
4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5
3.70 4.70 0.1 0.1
V V
4.5 5.5 IIN ICCT Maximum Input Leakage Current Maximum ICC/Input (Note 6) IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25°C is identical to 74ACT @ 25°C.
0.50 0.50
V µA mA
5.5 5.5
± 1.0
1.6
5.5 5.5 5.5
50 -50 40.0
mA mA µA
VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
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AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 8) fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V
54AC TA = -55°C to +125°C CL = 50 pF Min Max MHz 17.5 12.0 13.5 10.0 13.0 9.5 14.0 10.5 ns ns ns ns 65 95 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Units
Fig. No.
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
AC Operating Requirements
VCC Symbol Parameter (V) (Note 9) 54AC TA = -55°C to +125°C CL = 50 pF Guaranteed Minimum ts th tw trec Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn Pulse Width CDn or SDn or CPn Recovery Time CDn or SDn to CPn
Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V
Fig. Units No.
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
8.0 5.5 0 0.5 8.0 5.5 0.5 0.5
ns ns ns ns
5
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Others parts begin by 54
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