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Part: 54ACT399MW8
Category:
Logic
-> Military/Aerospace->FACT ACT
Description: 54ACT399 - Quad 2-Port Register, Package: Lcc, Pin Nb=20
Company: National Semiconductor Corporation
Datasheet: Download 54ACT399MW8 datasheet File size : 275 kB
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54ACT399 Quad 2-Port Register
August 1998
54ACT399 Quad 2-Port Register
General Description
The 'AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flop on the rising edge of the clock.
Features
n n n n n ICC reduced by 50% Select inputs from two data sources Fully positive edge-triggered operation Outputs source/sink 24 mA ACT399 has TTL-compatible inputs
Logic Symbols
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100356-1
IEEE/IEC
DS100356-3
Pin Assignment for LCC
DS100356-5
DS100356-2
Pin Names S CP I0a I 0d I1a I1d Qa Qd
Description Common Select Input Clock Pulse Input Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100356
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Functional Description
The 'AC/ACT399 is a high-speed quad 2-port register. It selects four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I0x, I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation.
Function Table
Inputs S L L H H I0 L H X X I1 X X L H CP
N N N N
Outputs Q L H L H Q H L H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition
Logic Diagram
DS100356-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND ) Storage Temperature (TSTG) -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Junction Temperature (TJ) CDIP
+175°C
Recommended Operating Conditions
Supply Voltage (VCC) 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
± 50 mA ± 50 mA -65°C to +150°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
DC Electrical Characteristics for 'ACT Family Devices
Symbol Parameter VCC (V) VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level 4.5 5.5 4.5 5.5 4.5 5.5 54ACT TA = -55°C to +125°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 2) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 (Note 2) VIN = VIL or VIH 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic (Note 3) Output Current Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Units
Conditions
V V V
VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA
V V
IOH = -24 mA IOH = -24 mA IOUT = 50 µA
0.50 0.50
V µA mA mA mA µA
IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VCC -2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or Ground
5.5 5.5 5.5 5.5 5.5
± 1.0
1.6 50 -50 80.0
3
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AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 4) Min fmax tPLH tPHL Input Clock Frequency Propagation Delay CP to Q Propagation Delay CP to Q
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V
54ACT TA, VCC = Mil CL = 50 pF Max
Fig. Units No.
5.0 5.0 5.0
90 1.5 1.5 10.0 10.0
MHz ns ns
AC Operating Requirements
VCC Symbol Parameter (V) (Note 5) 54ACT TA = -55°C to +125°C CL = 50 pF Guaranteed Minimum ts th ts th tw Setup Time, HIGH or LOW In to CP Hold Time, HIGH or LOW In to CP Setup Time, HIGH or LOW S to CP Hold Time, HIGH or LOW S to CP CP Pulse Width, HIGH or LOW
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Units
Fig. No.
5.0 5.0 5.0 5.0 5.0
3.5 3.0 6.0 2.5 5.0
ns ns ns ns ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF Conditions VCC = OPEN VCC = 5.0V
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4
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A
5
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