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Part: 54ACTQ374F
Category:
Logic
-> Flip-Flops
Description: Quiet Series Octal D Flip-flop With Tri-state Outputs
Company: National Semiconductor Corporation
Datasheet: Download 54ACTQ374F datasheet File size : 275 kB
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54ACQ374 · 54ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs
August 1998
54ACQ374 · 54ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE ® Outputs
General Description
The 'ACQ/'ACTQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The 'ACQ/'ACTQ374 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance. n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Buffered positive edge-triggered clock n TRI-STATE outputs drive bus lines or buffer memory address registers n Outputs source/sink 24 mA n Faster prop delays than the standard 'AC/'ACT374 n 4 kV minimum ESD immunity n Standard Military Drawing (SMD) -- 'ACTQ374: 5962-92189 -- 'ACQ374: 5962-92179
Features
n ICC and IOZ reduced by 50%
Logic Symbols
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100239-1
IEEE/IEC
DS100239-3
Pin Assignment for LCC
DS100239-2
DS100239-4
GTOTM is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet SeriesTM is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100239
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Connection Diagrams
(Continued) Pin Names Description Data Inputs Clock Pulse Input TRI-STATE Output Enable Input TRI-STATE Outputs
D0 D7 CP OE O0 O7
Functional Description
The 'ACQ/'ACTQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Truth Table
Inputs Dn H L X CP
N N
Outputs OE L L H On H L Z
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition
Logic Diagram
DS100239-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) CDIP -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Recommended Operating Conditions
Supply Voltage (VCC) 'ACQ 'ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACQ/ACTQ Minimum Input Edge Rate V/t 'ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate V/t 'ACTQ devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
125 mV/ns
± 50 mA ± 50 mA -65°C to +150°C ± 300 mA
175°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from -40°C to +125°C.
DC Characteristics for 'ACQ Family Devices
Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 54ACQ TA = -55°C to +125°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 3) VIN = VIL or VIH IOH = -12 mA V IOH = -24 mA IOH = -24 mA IOUT = 50 µA V IOUT = -50 µA V VOUT = 0.1V or VCC - 0.1V V VOUT = 0.1V or VCC - 0.1V Units Conditions
3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN Maximum Input Leakage Current IOLD IOHD (Note 4) Minimum Dynamic Output Current 5.5 5.5 5.5
2.4 3.7 4.7 0.1 0.1 0.1 0.50 0.50 0.50 V µA V
(Note 3) IOL = 12 mA IOL = 24 mA IOL = 24 mA VI = VCC, GND (Note 5)
± 1.0
50 -50
mA mA
VOLD = 1.65V Max VOHD = 3.85V Min
3
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DC Characteristics for 'ACQ Family Devices
Symbol ICC IOZ Parameter Maximum Quiescent Supply Current Maximum TRI-STATE Leakage Current VOLP VOLV Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
VCC (V) 5.5
54ACQ TA = -55°C to +125°C Guaranteed Limits 80.0
Units µA
Conditions VIN = VCC or GND (Note 5) VI(OE) = VIL, VIH VI = VCC, GND VO = VCC, GND
5.5 5.0 5.0
± 5.0
1.5 -1.2
µA V
(Notes 6, 7) V (Notes 6, 7)
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54ACQ @ 25°C is identical to 74ACQ @ 25°C. Note 6: Plastic DIP Package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 8: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 5V ('ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
DC Characteristics for 'ACTQ Family Devices
Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 54ACTQ TA = -55°C to +125°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 (Note 9) VIN = VIL or VIH IOH = -24 mA IOH = -24 mA IOUT = 50 µA (Note 9) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA Units Conditions
4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5
3.70 4.70 0.1 0.1
V V
4.5 5.5 IIN IOZ ICCT IOLD IOHD Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC/Input (Note 9) Minimum Dynamic Output Current 5.5 5.5 5.5 5.5 5.5
0.50 0.50
V µA µA mA mA mA
± 1.0 ± 5.0
1.6 50 -50
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DC Characteristics for 'ACTQ Family Devices
Symbol ICC VOLP VOLV Parameter Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL
Note 9: All outputs loaded; thresholds on input associated with output under test. Note 10: Maximum test duration 2.0 ms, one output loaded at a time. Note 11: ICC for 54ACTQ @ 25°C is identical to 74ACTQ @ 25°C. Note 12: Plastic DIP package.
(Continued)
VCC (V) 5.5 5.0 5.0
54ACTQ TA = -55°C to +125°C Guaranteed Limits 80.0 1.5 -1.2
Units µA V
Conditions VIN = VCC or GND (Note 11) (Notes 12, 13)
V (Notes 12, 13)
Note 13: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND Note 14: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 3V ('ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 15) fmax tPLH, tPHL tPZL, tPZH tPHZ, tPLZ Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V
54ACQ TA = -55°C to +125°C CL = 50 pF Min 95 95 1.0 1.0 1.0 1.0 1.0 1.0 16.5 11.0 16.5 11.5 12.0 10.5 ns ns ns Max MHz Units
Fig. No.
AC Operating Requirements
VCC Symbol Parameter (V) (Note 16) 54ACQ TA = -55°C to +125°C CL = 50 pF Guaranteed Minimum ts th tw Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V
Fig. Units No.
3.3 5.0 3.3 5.0 3.3 5.0
3.0 3.0 2.0 1.5 5.0 5.0
ns ns ns
5
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