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Part: 54F169DM
Category:
Logic
-> Military/Aerospace->FAST
Description: 54F169 - 4-State Synchronous Bidirectional Counter, Package: Lcc, Pin Nb=20
Company: National Semiconductor Corporation
Datasheet: Download 54F169DM datasheet File size : 275 kB
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Datasheet text preview:
54F 74F169 4-Stage Synchronous Bidirectional Counter
November 1994
54F 74F169 4-Stage Synchronous Bidirectional Counter
General Description
The 'F169 is a fully synchronous 4-stage up down counter he 'F169 is a modulo-16 binary counter Features a preset capability for programmable operation carry lookahead for easy cascading and a U D input to control the direction of counting All state changes whether in counting or parallel loading are initiated by the LOW-to-HIGH transition of the clock
Y Y Y
eatures
Asynchronous counting and loading Built-in lookahead carry capability Presettable for programmable operation
F
Commercial 74F169PC
Military
Package Number N16E
Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ
54F169DM (Note 2) 74F169SC (Note 1) 74F169SJ (Note 1)
J16A M16A M16D
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX L ote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB
ogic Symbols
IEEE IEC 'F169
TL F 9488 3
TL F 9488 9
C TRI-STATE is a registered trademark of National Semiconductor Corporation
1995 National Semiconductor Corporation
TL F 9488
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9488 1
TL F 9488 2
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 20 10 10 10 10 10 10 10 10 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA b 1 mA 20 mA
CEP CET CP P0 P3 PE UD Q0 Q3 TC
Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output (Active LOW)
Functional Description
The 'F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter The parallel load operation takes precedence over other operations as indicated in the Mode Select Table When PE is LOW the data on the P0 P3 inputs enters the flip-flops on the next rising edge of the clock In order for counting to occur both CEP and CET must be LOW and PE must be HIGH the U D input then determines the direction of counting The Terminal Count (TC) output is normally HIGH and goes LOW provided that CET is LOW when a counter reaches zero in the Count Down mode or reaches 15 for the 'F169 in the Count Up mode The TC output state is not a function of the Count Enable Parallel (CEP) input level Since the TC signal is derived by decoding the flip-flop states there exists the possibility of decoding spikes on TC For this reason the use of TC as a clock signal is not recommended (see logic equa1 tions below) ) Count Enable e CEP CET PE 2) Up ('F169) TC e Q0 Q1 Q2 Q3 (Up) CET 3) Down TC e Q0 Q1 Q2 Q3 (Down) CET
2
Logic Diagram
'F169
TL F 9488 5
Please note that these diagrams are prMided only for the understanding of logic operations and should not be used to estimate propagation delays ov
ode Select Table PE L H H H H CEP X L L H X CET X L L X H UD X H L X X Action on Rising Clock Edge Load (Pn x Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold)
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial
State Diagram
'F169
TL F 9488 7
3
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max)
ecommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
b 0 5V to VCC b 0 5V to a 5 5V
twice the rated IOL (mA)
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied ote 2 Either voltage limit or current limit is sufficient to protect inputs R
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current
b 60
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V V Min Min
IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (except CET) VIN e 0 5V (CET) VOUT e 0V VO e LOW
54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F
25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75
b0 6 b1 2 b 150
VOL IIH IBVI ICEX VID IOD IIL IOS ICCL
V mA mA mA V mA mA mA mA
Min Max Max Max 00 00 Max Max Max
35
52
4
'F169 AC Electrical Characteristics
74F Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE HIGH or LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U D to TC 90 30 40 55 40 25 25 35 40 65 90 12 0 85 45 85 85 80 85 11 5 15 5 12 5 65 11 0 11 5 12 0 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ Max 54F TA VCC e Mil CL e 50 pF Min 60 30 40 55 40 25 25 35 40 12 0 16 0 20 0 15 0 90 12 0 16 0 14 0 Max 74F TA VCC e Com CL e 50 pF Min 70 30 40 55 40 25 25 35 40 95 13 0 17 5 13 0 70 12 0 12 5 13 0 Max MHz ns ns ns ns Units
AC Operating Requirements
74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup Time HIGH or LOW Pn to CP Hold Time HIGH or LOW Pn to CP Setup Time HIGH or LOW CEP or CET to CP Hold Time HIGH or LOW CEP or CET to CP Setup Time HIGH or LOW PE to CP Hold Time HIGH or LOW PE to CP Setup Time HIGH or LOW U D to CP Hold Time HIGH or LOW U D to CP CP Pulse Width HIGH or LOW 40 40 30 30 70 50 0 05 80 80 10 0 11 0 70 0 0 40 70 Max 54F TA VCC e Mil Min 45 45 35 35 80 80 0 10 10 0 10 0 10 0 14 0 12 0 0 0 60 90 Max 74F TA VCC e Com Min 45 45 35 35 80 65 0 05 90 90 10 0 12 5 85 0 0 45 80 ns Max Units
ns
ns
ns
ns
5
Others parts begin by 54
54-1 54-2 54-3 54-4 54-5 54-6 54-7 54-8 54-9 54-10 54-11 54-12 54-13
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