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Part: 54F174FM
Category:
Logic
-> Flip-Flops
Description: Hex D Flip-flop With Master Reset
Company: National Semiconductor Corporation
Datasheet: Download 54F174FM datasheet File size : 275 kB
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Datasheet text preview:
54F 74F174 Hex D Flip-Flop with Master Reset
November 1994
54F 74F174 Hex D Flip-Flop with Master Reset
General Description
The 'F174 is a high-speed hex D flip-flop The device is T used primarily as a 6-bit edge-triggered storage register he information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition The device has a Master Reset to simultaneously clear all flip-flops
Y Y Y Y
eatures
Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous common reset Guaranteed 4000V minimum ESD protection
F
Commercial 74F174PC
Military
Package Number N16E
Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F174DM (Note 2) 74F174SC (Note 1) 74F174SJ (Note 1) 54F174FM (Note 2) 54F174LM (Note 2)
J16A M16A M16D W16A E20A
Note 1 Devices also available in 13 reel Use Suffix e SCX and SJX L ote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
ogic Symbols
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9489 3 TL F 9489 1 TL F 9489 2
IEEE IEC
TL F 9489 5
C TRI-STATE is a registered trademark of National Semiconductor Corporation
1995 National Semiconductor Corporation
TL F 9489
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA b 1 mA 20 mA
D0 D5 CP MR Q0 Q5
Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs
Functional Description
The 'F174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs The Clock (CP) and Master Reset (MR) are common to all flip-flops Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs The 'F174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements
ruth Table
Inputs MR L H H CP X L L Dn X H L Outputs Qn L H L
H e HIGH Voltage Level L e LOW Voltage Level
Te X
Immaterial
L e LOW-to-HIGH Clock Transition
Logic Diagram
TL F 9489 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min)
ecommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
b 0 5V to VCC b 0 5V to a 5 5V
twice the rated IOL (mA) 4000V
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied ote 2 Either voltage limit or current limit is sufficient to protect inputs R
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current
b 60
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V V Min Min
IIN e b18 mA IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V VOUT e 0V CP e L Dn e MR e HIGH VO e LOW
54F 10% VCC 74F 10% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F
25 25 27 05 05 20 0 50 100 70 250 50 4 75 3 75
b0 6 b 150
VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL
V mA mA mA V mA mA mA mA mA
Min Max Max Max 00 00 Max Max Max Max
30 30
45 45
3
AC Electrical Characteristics
74F Symbol Parameter Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn 80 35 40 50 55 70 10 0 80 10 0 14 0 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ Max 54F TA VCC e Mil CL e 50 pF Min 70 30 40 50 10 0 12 0 16 0 Max 74F TA VCC e Com CL e 50 pF Min 80 35 40 50 90 11 0 15 0 Max MHz ns ns Units
AC Operating Requirements
74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP 48 40 0 0 40 60 50 50 Max 54F TA VCC e Mil Min 50 50 20 20 50 75 65 60 Max 74F TA VCC e Com Min 48 40 0 0 40 60 50 50 ns ns Max Units
ns
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 7 4F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SS e Small Outline SOIC EIAJ 174 S C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13 reel Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C)
Physical Dimensions inches (millimeters)
20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A
5
Others parts begin by 54
54-1 54-2 54-3 54-4 54-5 54-6 54-7 54-8 54-9 54-10 54-11 54-12 54-13
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