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Part: 54F175FM-MLS
Category:
Logic
-> Military/Aerospace->Low Power Schottky
Description: DM54LS175 - Quad D Flip-flop With Clear And Complementary Outputs, Package: Cerpack, Pin Nb=16
Company: National Semiconductor Corporation
Datasheet: Download 54F175FM-MLS datasheet File size : 275 kB
Request For quote: Find where to buy 54F175FM-MLS
Datasheet text preview:
54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear
June 1989
54LS174 DM54LS174 DM74LS174 4LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary I outputs from each flip-flop nformation at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output C
Y Y
eatures
LS174 contains six flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Y Buffered clock and direct clear inputs Y Individual data input to each flip-flop Y Applications include B uffer storage registers Shift registers Pattern generators Y Typical clock frequency 40 MHz Y Typical power dissipation per flip-flop 14 mW F Y Alternate 5 Military Aerospace device (54LS174 4LS175) is available Contact a National Semiconductor Sales Office Distributor for specifications
onnection Diagrams
Dual-In-Line Package Dual-In-Line Package
TL F 6404 1
TL F 6404 2
Order Number 54LS174DMQB 54LS174FMQB 54LS174LMQB DM54LS174J DM54LS174W DM74LS174M or DM74LS174N See NS Package Number E20A J16A M16A N16E or W16A
Order Number 54LS175DMQB 54LS175FMQB 54LS175LMQB DM54LS175J DM54LS175W DM74LS175M or DM74LS175N See NS Package Number E20A J16A M16A N16E or W16A
Function Table (Each Flip-Flop)
Inputs
L Clear
Outputs D X H L X Q L H L Q0 Q H L H Q0
H e High Level (steady state) L e Low Level (steady state) X e Don't Care
Clock X
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were e established LS175 only
H H H
u u
L
C1995 National Semiconductor Corporation
TL F 6404
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage Input Voltage 7V 7V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings T he ``Recommended Operating Conditions'' table will define the conditions for actual device operation
Operating Free Air Temperature Range R b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C Storage Temperature Range
b 65
C to a 150 C
ecommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW tSU tH tREL TA Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 1) Clock Frequency (Note 2) Pulse Width (Note 6) Clock Clear 0 0 20 20 20 0 25
b 55
DM54LS174 Nom 5 Max 55 07
b0 4
DM74LS174 Min 4 75 2 08
b0 4
Units Max 5 25 V V V mA mA MHz MHz ns ns ns ns 70
Nom 5
45 2
4 30 25 0 0 20 20 20 0 25 125 0
8 30 25
Data Setup Time (Note 6) Data Hold Time (Note 6) Clear Release Time (Note 6) Free Air Operating Temperature
C
'LS174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II IIH IIL Input Current Input Voltage
Max
Min
Typ (Note 3) 34 34 0 25 0 35 0 25
Max
b1 5
Units V V
DM54 DM74 DM54 DM74 DM74
25 27
04 05 04 01 20 mA mA mA V
VCC e Max VI e 7V VCC e Max VI e 2 7V VCC e Max VI e 0 4V Clock Clear Data DM54 DM74
b 20 b 20
High Level Input Current Low Level Input Current
b0 4 b0 4 b 0 36 b 100 b 100
IOS ICC
Short Circuit Output Current Supply Current
VCC e Max (Note 4) VCC e Max (Note 5)
mA mA
16
26
Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V Note 3 All typicals are at VCC e 5V TA e 25 C Note 4 Not more than one output should be shorted at a time and the duration should not exceed one second Note 5 With all outputs open and 4 5V applied to all data and clear inputs ICC is measured after a momentary ground then 4 5V applied to the clock ote 6 TA e 25 C and VCC e 5V 2
'LS174 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) RL e 2 kX CL e 15 pF Min fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Output Clock to Output Clear to Output 30 30 30 35 Max CL e 50 pF Min 25 32 36 42 Max MHz ns ns ns Units
Symbol
Parameter
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 1) Clock Frequency (Note 2) Pulse Width (Note 3) Clock Clear 0 0 20 20 20 0 25
b 55
DM54LS175 Nom 5 Max 55 Min 4 75 2 07
b0 4
DM74LS175 Nom 5 Max 5 25
Units V V 08
b0 4
45 2
V mA mA MHz MHz ns ns ns ns
4 30 25 0 0 20 20 20 0 25 125 0
8 30 25
tSU tH tREL TA
Data Setup Time (Note 3) Data Hold Time (Note 3) Clear Release Time (Note 3) Free Air Operating Temperature
70
C
Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V ote 3 TA e 25 C and VCC e 5V 3
'LS175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIL e Max VIH e Min IOL e 4 mA VCC e Min II IIH IIL Input Current Input Voltage
Max
Min
Typ (Note 1)
Max
b1 5
Units V V
DM54 DM74 DM54 DM74 DM74
25 27
34 34 0 25 0 35 0 25 04 05 04 01 20
VOL
V
VCC e Max VI e 7V VCC e Max VI e 2 7V VCC e Max VI e 0 4V Clock Clear Data
mA mA
High Level Input Current Low Level Input Current
b0 4 b0 4 b 0 36 b 20 b 20 b 100 b 100
mA
IOS
Short Circuit Output Current Supply Current
VCC e Max (Note 2) VCC e Max (Note 3)
DM54 DM74
mA mA
ICC
11
18
'LS175 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) RL e 2 kX CL e 15 pF Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Clock to Q or Q Clock to Q or Q Clear to Q Clear to Q 30 30 30 25 35 Max CL e 50 pF Min 25 32 36 29 42 Max MHz ns ns ns ns Units
Symbol
Parameter
Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second ote 3 With all outputs open and 4 5V applied to all data and clear inputs ICC4s measured after a momentary ground then 4 5V applied to the clock input i
Logic Diagrams
LS174 LS175
TL F 6404 4
TL F 6404 3
5
Others parts begin by 54
54-1 54-2 54-3 54-4 54-5 54-6 54-7 54-8 54-9 54-10 54-11 54-12 54-13
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