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Part: 54F322FMQB
Category:
Logic
-> Military/Aerospace->FAST
Description: 54F322 - Octal Serial/parallel Register With Sign Extend, Package: Cerdip, Pin Nb=20
Company: National Semiconductor Corporation
Datasheet: Download 54F322FMQB datasheet File size : 222 kB
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54F 74F322 Octal Serial Parallel Register with Sign Extend
May 1995
54F 74F322 Octal Serial Parallel Register with Sign Extend
General Description
The 'F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATE parallel outputs plus a bi-state serial output Parallel data inputs and parallel outputs are multiplexed to minimize pin count State changes are initiated by the rising edge of the clock Four synchronous modes of operation are possible hold (store) hift right with serial entry shift right with sign extend and parallel load An asynchronous Master Reset (MR) input overrides clocked operation and clears the register
Y Y Y Y
eatures
Multiplexed parallel I O ports Separate serial input and output Sign extend function TRI-STATE outputs for bus applications
F
Commercial 74F322PC
Military
Package Number N20A
Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F322DM (Note 2) 74F322SJ (Note 1) 54F322FM (Note 2) 54F322LM (Note 2)
Note 1 Devices also available in 13 reel Use suffix e SJX L
J20A M20D W20A E20A
ote 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
ogic Symbols
IEEE IEC
TL F 9516 3
TL F 9516 5
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL F 9516 RRD-B30M105 Printed in U S A
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9516 2 TL F 9516 1
2
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW Input IIH IIL Output IOH IOL
RE SP SE S D0 D1 CP MR OE Q0 I O0 I O7
Register Enable Input (Active LOW) 10 10 20 mA b0 6 mA Serial (HIGH) or Parallel (LOW) Mode Control Input 10 10 20 mA b0 6 mA Sign Extend Input (Active LOW) 10 30 20 mA b1 8 mA Serial Data Select Input 10 20 20 mA b1 2 mA Serial Data Inputs 10 10 20 mA b0 6 mA Clock Pulse Input (Active Rising Edge) 10 10 20 mA b0 6 mA Asynchronous Master Reset Input (Active LOW) 10 10 20 mA b0 6 mA TRI-STATE Output Enable Input (Active LOW) 10 10 20 mA b0 6 mA b 1 mA b20 mA Bi-State Serial Output 50 33 3 Multiplexed Parallel Data Inputs or 3 5 1 083 70 mA b0 65 mA TRI-STATE Parallel Data Outputs 150 40 (33 3) b3 mA 24 mA (20 mA)
Functional Description
The 'F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations A LOW signal on RE enables shifting or parallel loading while a HIGH signal enables the hold mode A HIGH signal on S P enables shift right while a M LOW signal disables the TRI-STATE output buffers and enables parallel loading In the shift right mode a HIGH signal on SE enables serial entry from either D0 or D1 as determined by the S input A LOW signal on SE enables shift right but Q7 reloads its contents thus performing the sign extend A function required for the 'F384 Twos Complement Multiplier HIGH signal on OE disables the TRI-STATE output buffers regardless of the other control inputs In this condition the shifting and loading operations can still be performed
ode Select Table Mode MR Clear Parallel Load Shift Right Sign Extend Hold L L H H H H H RE X X L L L L H SP X X L H H H X Inputs SE X X X H H L X S X X X L H X X OE L H X L L L L CP X X L L L L L I O7 L Z I7 D0 D1 O7 NC I O6 L Z I6 O7 O7 O7 NC I O5 L Z I5 O6 O6 O6 NC Outputs I O4 L Z I4 O5 O5 O5 NC I O3 L Z I3 O4 O4 O4 NC I O2 L Z I2 O3 O3 O3 NC I O1 L Z I1 O2 O2 O2 NC I O0 L Z I0 O1 O1 O1 NC L L I0 O1 O1 O1 NC Q0
N When the OE input is HIGH all I On terminals are at the high impedance state sequential operation or clearing of the register is not affected ote 1 I7 I0 e The level of the steady-state input at the respective I O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from N the I O terminal Note 2 D0 D1 e The level of the steady-state inputs to the serial multiplexer input Hote 3 O7 O0 e The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance Output State L e LOW-to-HIGH Transition NC e No Change
3
Logic Diagram
TL F 9516 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 4
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) oltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max)
b 0 5V to VCC b 0 5V to a 5 5V
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
twice the rated IOL (mA)
Recommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military V Commercial
b 55
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied ote 2 Either voltage limit or current limit is sufficient to protect inputs
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75
b0 6 b1 2 b1 8
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V Min
IIN e b18 mA IOH IOH IOH IOH IOH IOH
e e e e e e b 1 mA (Q0 I On) b 3 mA (I On) b 1 mA (Q0 I On) b 3 mA (I On) b 1 mA (Q0 I On) b 3 mA (I On)
25 24 25 24 27 27 05 05 05 20 0 50 100 70 10 05 250 50
V
Min
VOL
Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current
V
Min
IOL e 20 mA (Q0 I On) IOL e 20 mA (Q0) IOL e 24 mA ( I On) VIN e 2 7V VIN e 7 0V (Non-I O Inputs) VIN e 5 5V (I On) VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (RE S P Dn CP MR OE) VIN e 0 5V (S) VIN e 0 5V (SE) VI O e 2 7V (I On) VI O e 0 5V (I On) VOUT e 0V VOUT e 5 25V
IIH IBVI IBVIT ICEX VID IOD IIL
mA mA mA mA V mA mA mA mA mA mA mA mA mA
Max Max Max Max 00 00 Max Max Max Max Max Max 0 0V Max
IIH a IOZH IIL a IOZL IOS IZZ ICC
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 60
b 60
70
b 650 b 150
500 90
5
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