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Part: 54F823LMQB
Category:
Logic
-> Military/Aerospace->FAST
Description: 54F823 - 9-Bit D Flip-Flop, Package: Lcc, Pin Nb=28
Company: National Semiconductor Corporation
Datasheet: Download 54F823LMQB datasheet File size : 180 kB
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Datasheet text preview:
54F 74F823 9-Bit D-Type Flip-Flop
December 1994
54F 74F823 9-Bit D-Type Flip-Flop
General Description
The 'F823 is a 9-bit buffered register It features Clock Enable and Clear which are ideal for parity bus interfacing in T high performance microprogramming systems he 'F823 is functionally and pin compatible with AMD's Am29823
Y Y Y
eatures
TRI-STATE outputs Clock Enable and Clear Direct replacement for AMD's Am29823
F
Commercial 74F823SPC
Military
Package Number N24C
Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Cerpack 24-Lead Ceramic Chip Carrier Type C
54F823SDM (Note 2) 74F823SC (Note 1) 54F823FM (Note 2) 54F823LM (Note 2)
Note 1 Devices also available in 13 reel Use suffix e SCX
J24F M24B W24C E28A
o L te 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB
ogic Symbols
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 9596 2
IEEE IEC
TL F 9596 4 TL F 9596 3
TL F 9596 1
C TRI-STATE is a registered trademark of National Semiconductor Corporation
1995 National Semiconductor Corporation
TL F 9596
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 10 20 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA b 3 mA 24 mA (20 mA)
D0 D8 OE CLR CP EN O0 O8
Data Inputs Output Enable Input Clear Clock Input Clock Enable TRI-STATE Outputs
2
Functional Description
The 'F823 device consists of nine D-type edge-triggered flip-flops It has TRI-STATE true outputs and is organized in broadside pinning The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops The flipflops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition With the OE LOW the contents of the flipflops are available at the outputs When the OE is HIGH the outputs go to the high impedance state Operation of F he t OE input does not affect the state of the flip-flops In addition to the Clock and Output Enable pins the 'F823 has Cl Wear (CLR) and Clock Enable (EN) pins hen the CLR is LOW and the OE is LOW the outputs are LOW When CLR is HIGH data can be entered into the flipflops When EN is LOW data on the inputs is transferred to the outputs on the LOW to HIGH clock transition When the EN is HIGH the outputs do not change state regardless of the data or clock inputs transitions This device is ideal for parity bus interfacing in high performance systems
unction Table Inputs OE H H H L H L H H L L L L CLR H H H H L L H H H H H H EN L L H H X X L L L L L L CP H L X X X X L L L L H L D X X X X X X H H L H X X Internal Q NC NC NC NC H H H L H L NC NC Output O Z Z Z NC Z L Z Z L H NC NC Hold Hold Hold Hold Clear Clear Load Load Data Available Data Available No Change in Data No Change in Data Function
L e LOW Voltage Level H e HIGH Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change
Logic Diagram
TL F 9596 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max)
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under N these conditions is not implied Rte 2 Either voltage limit or current limit is sufficient to protect inputs o
C to a 150 C b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C
b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA
b 65
ecommended Operating Conditions
Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
b 55
C to a 125 C 0 C to a 70 C
a 4 5V to a 5 5V a 4 5V to a 5 5V
b 0 5V to VCC b 0 5V to a 5 5V
twice the rated IOL (mA)
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Output HIGH Voltage Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74F 54F 74F 54F 74F 74F 74F 4 75 3 75
b0 6 b1 2
54F 74F Typ Max
Units V 08
b1 2
VCC
Conditions Recognized as a HIGH Signal Recognized as a LOW Signal
20
V V Min
IIN e b18 mA IOH IOH IOH IOH IOH IOH
e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA
25 24 25 24 27 27 05 05 20 0 50 100 70 250 50
V
Min
VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ
Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current
V mA mA mA V mA mA mA mA mA mA mA mA
Min Max Max Max 00 00 Max Max Max Max Max 0 0V Max
IOL e 20 mA IOL e 24 mA VIN e 2 7V VIN e 7 0V VOUT e VCC IID e 1 9 mA All Other Pins Grounded VIOD e 150 mV All Other Pins Grounded VIN e 0 5V (OE CLR EN) VIN e 0 5V (CP) VOUT e 2 7V VOUT e 0 5V VOUT e 0V VOUT e 5 25V VO e HIGH Z
Output Leakage Current Output Leakage Current Output Short-Circuit Current Buss Drainage Test Power Supply Current 75
b 60
50
b 50 b 150
500 100
4
AC Electrical Characteristics
74F Symbol Parameter Min fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CLR to On Output Enable Time OE to On Output Disable Time OE to On 100 20 20 40 20 20 15 15 TA e a 25 C VCC e a 5 0V CL e 50 pF Typ 160 56 52 71 58 55 29 27 95 95 12 0 10 5 10 5 70 70 Max 54F TA VCC e Mil CL e 50 pF Min 60 20 20 40 20 20 10 10 10 5 10 5 13 0 13 0 13 0 75 75 Max 74F TA VCC e Com CL e 50 pF Min 70 20 20 40 20 20 15 15 10 5 10 5 13 0 11 5 11 5 75 75 Max MHz ns ns Units
ns
AC Operating Requirements
74F Symbol Parameter TA e a 25 C VCC e a 5 0V Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Setup Time HIGH or LOW EN to CP Hold Time HIGH or LOW EN to CP CP Pulse Width HIGH or LOW CLR Pulse Width LOW CLR Recovery Time 25 25 25 25 45 25 20 0 50 50 50 50 Max 54F TA VCC e Mil Min 40 40 25 25 50 30 30 10 60 60 50 50 Max 74F TA VCC e Com Min 30 30 25 25 50 30 20 0 60 60 50 50 ns ns ns Max Units
ns
ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 7 4F Temperature Range Family 74F e Commercial 54F e Military Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline (SOIC) 823 S C X Special Variations QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C)
5
Others parts begin by 54
54-1 54-2 54-3 54-4 54-5 54-6 54-7 54-8 54-9 54-10 54-11 54-12 54-13
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