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Part: 5962-8752101VA
Category:
Description: MM54C922 - 16-Key Encoder Life-time Buy , Package: Cerdip, Pin Nb=18
Company: National Semiconductor Corporation
Datasheet: Download 5962-8752101VA datasheet File size : 231 kB
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Datasheet text preview:
MM54C922 MM74C922 16-Key Encoder MM54C923 MM74C923 20-Key Encoder
July 1993
MM54C922 MM74C922 16-Key Encoder MM54C923 MM74C923 20-Key Encoder
General Description
These CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches The keyboard scan can be implemented by either an external clock or external capacitor These encoders also have on-chip pullup devices which permit switches with up to 50 kX on resistance to be used No diodes in the switch array are needed to eliminate ghost switches The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor A Data Available output goes to a high level when a valid keyboard entry has been made The Data Available output returns to a low level when the entered key is released even if another key is depressed The Data Available will return high to indicate acceptance of the new key after a normal debounce period this two-key rollover is provided between any two switches n internal register remembers the last key pressed even after the key is released The TRI-STATE outputs provide for easy expansion and bus operation and are LPTTL compatible F
eatures
50 kX maximum switch on resistance On or off chip clock Y On-chip row pull-up devices Y 2 key roll-over Y Keybounce elimination with single capacitor Y Last key register at outputs Y TRI-STATE outpust LPTTL compatible Y Wide supply range A Y Low power consumption
Y Y
3V to 15V
Connection Diagrams
Pin Assignment for Dual-In-Line Package Pin Assignment for SOIC Pin Assignment for DIP and SOIC Package
TL F 6037 14
Top View
TL F 6037 1
Order Number MM74C922
TL F 6037 2
Top View Order Number MM54C922 or MM74C922 Top View
Order Number MM54C923 or MM74C923
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL F 6037 RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note 1)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales V Office Distributors for availability and specifications oltage at Any Pin Operating Temperature Range MM54C922 MM54C923 MM74C922 MM74C923 VCC b 0 3V to VCC a 0 3V
b 55 C to a 125 b 40 C to a 85
Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range VCC Lead Temperature (Soldering 10 seconds)
b 65
C to a 150 C
700 mW 500 mW 3V to 15V 18V 260 C
C C
DC Electrical Characteristics Min
Symbol CMOS TO CMOS VT a Positive-Going Threshold Voltage at Osc and KBM Inputs Negative-Going Threshold Voltage at Osc and KBM Inputs Logical ``1'' Input Voltage Except Osc and KBM Inputs Logical ``0'' Input Voltage Except Osc and KBM Inputs Row Pull-Up Current at Y1 Y2 Y3 Y4 and Y5 Inputs Logical ``1'' Output Voltage Parameter
Max limits apply across temperature range unless otherwise specified Conditions Min 30 60 90 07 14 21 35 80 12 5 Typ 36 68 10 14 32 5 45 9 13 5 05 1 15
b2 b 10 b 22
Max 43 86 12 9 20 40 60
Units V V V V V V V V V
VCC e 5V IIN t 0 7 mA VCC e 10V IIN t 1 4 mA VCC e 15V IIN t 2 1 mA VCC e 5V IIN t 0 7 mA VCC e 10V IIN t 1 4 mA VCC e 15V IIN t 2 1 mA VCC e 5V VCC e 10V VCC e 15V VCC e 5V VCC e 10V VCC e 15V VCC e 5V VIN e 0 1 VCC VCC e 10V VCC e 15V VCC e 5V IO e b10 mA VCC e 10V IO e b10 mA VCC e 15V IO e b10 mA VCC e 5V IO e 10 mA VCC e 10V IO e 10 mA VCC e 15V IO e 10 mA VCC e 5V VO e 0 5V VCC e 10V VO e 1V VCC e 15V VO e 1 5V VCC e 5V VCC e 10V VCC e 15V VCC e 15V VIN e 15V VCC e 15V VIN e 0V
VTb
VIN(1)
VIN(0)
15 2 25
b5 b 20 b 45
V V V mA mA mA V V V
Irp
VOUT(1)
45 9 13 5 05 1 15 500 300 200 0 55 11 17 0 005
b1 0 b 0 005
VOUT(0)
Logical ``0'' Output Voltage
V V V X X X mA mA mA mA mA
Ron
Column ``ON'' Resistance at X1 X2 X3 and X4 Outputs Supply Current Osc at 0V (one Y low) Logical ``1'' Input Current at Output Enable Logical ``0'' Input Current at Output Enable Logical ``1'' Input Voltage Except Osc and KBM Inputs Logical ``0'' Input Voltage Except Osc and KBM Inputs Logical ``1'' Output Voltage
1400 700 500 11 19 26 10
ICC
IIN(1) IIN(0)
CMOS LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA VCC b 1 5 VCC b 1 5 08 08 24 24 04 04 V V V V V V V V
VOUT(0)
Logical ``0'' Output Voltage
Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation 2
DC Electrical Characteristics
Min Max limits apply across temperature range unless otherwise specified (Continued) Symbol ISOURCE ISOURCE ISINK ISINK Parameter Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) Conditions VCC e 5V VOUT e 0V TA e 25 C VCC e 10V VOUT e 0V TA e 25 C VCC e 5V VOUT e VCC TA e 25 C VCC e 10V VOUT e VCC TA e 25 C Min b Typ Max Units OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current) 1 75 8
b3 3 b 15
mA mA mA mA
b 1
75 8
36 16
AC Electrical Characteristics TA e 25 C
Symbol tpd0 tpd1 Parameter Propagation Delay Time to Logical ``0'' or Logical ``1'' from D A Propagation Delay Time from Logical ``0'' or Logical ``1'' into High Impedance State Propagation Delay Time from High Impedance State to a Logical ``0'' or Logical ``1'' Input Capacitance TRI-STATE Output Capacitance
CL e 50 pF unless otherwise noted Conditions Min Typ 60 35 25 80 65 50 100 55 40 5 10 Max 150 80 60 200 150 110 250 125 90 75 Units ns ns ns ns ns ns ns ns ns pF pF
CL e 50 pF (Figure 1) VCC e 5V VCC e 10V VCC e 15V RL e 10k CL e 10 pF (Figure 2) VCC e 5V RL e 10k VCC e 10V CL e 10 pF VCC e 15V RL e 10k CL e 50 pF (Figure 2) VCC e 5V RL e 10k VCC e 10V CL e 50 pF VCC e 15V Any Input (Note 2) Any Output (Note 2)
t0H t1H
tH0 tH1
CIN COUT
N Parameters are guaranteed by DC correlated testing AC ote 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device N operation S te 2 Capacitance is guaranteed by periodic testing o
witching Time Waveforms
TL F 6037 4 TL F 6037 3
FIGURE 2
T1
T2
RC T3
0 7 RC where F R
10k and C is external capacitor at KBM input
IGURE 1 3
Block Diagram
TL F 6037 5
Truth Table
Switch Position D A T A O U T A B C D E 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Y1 X1 Y1 X2 Y1 X3 Y1 X4 Y2 X1 Y2 X2 Y2 X3 Y2 X4 Y3 X1 Y3 X2 Y3 X3 Y3 X4 Y4 X1 Y4 X2 Y4 X3 Y4 X4 Y5 X1 Y5 X2 Y5 X3 Y5 X4
0 0 0 0 0
1 0 0 0 0
0 1 0 0 0
1 1 0 0 0
0 0 1 0 0
1 0 1 0 0
0 1 1 0 0
1 1 1 0 0
0 0 0 1 0
1 0 0 1 0
0 1 0 1 0
1 1 0 1 0
0 0 1 1 0
1 0 1 1 0
0 1 1 1 0
1 1 1 1 0
0 0 0 0 1
1 0 0 0 1
0 1 0 0 1
1 1 0 0 1
Omit for MM54C922 MM74C922
4
Typical Performance Characteristics
Typical Irp vs VIN at Any Y Input Typical Ron vs VOUT at Any X Output
TL F 6037 6
TL F 6037 7
Typical FSCAN vs COSC
Typical Debounce Period vs CKBM
TL F 6037 8
TL F 6037 9
Typical Applications
Synchronous Handshake (MM74C922) Synchronous Data Entry Onto Bus (MM74C922)
TL F 6037 10 TL F 6037 11
N
Outputs are enabled when valid entry is made and go into TRI-STATE when key is released
ote 3 The keyboard may be synchronously scanned by omitting the capacitor at osc and driving osc directly if the system clock rate is lower than 10 kHz 5
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
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