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Part: 5962-88520012A
Category:
Logic
-> Military/Aerospace->FACT AC
Description: 54AC74 - Dual D-type Positive Edge-triggered Flip-Flop, Package: Lcc, Pin Nb=20
Company: National Semiconductor Corporation
Datasheet: Download 5962-88520012A datasheet File size : 224 kB
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Datasheet text preview:
54AC74/54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
July 2003
54AC74/54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 'AC/'ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
ICC reduced by 50% Output source/sink 24 mA 'ACT74 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) -- 'AC74: 5962-88520 -- 'ACT74: 5962-87525 n 54AC74 now qualified to 300Krad RHA designation, refer to the SMD for more information n n n n
Logic Symbols
10026601
10026602
IEEE/IEC D 1, D 2
Pin Names CP1, CP2 CD1, CD2 SD1, SD2 Q 1, Q 1, Q 2, Q 2
Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
10026603
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS100266
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54AC74/54ACT74
Connection Diagrams
Pin Assignment for DIP and Flatpak Pin Assignment for LCC
10026604
10026605
Truth Table
(Each Half) Inputs SD L H L H H H CD H L L H H H CP X X X
N N
Outputs D X X X H L X Q H L H H L Q0 Q L H H L H Q0
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
10026606
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
54AC74/54ACT74
Absolute Maximum Ratings
(Note 1)
'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP 175°C -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
125 mV/ns
125 mV/ns
± 50 mA ± 50 mA
-65°C to +150°C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
Recommended Operating Conditions
Supply Voltage (VCC) 'AC 2.0V to 6.0V
DC Characteristics for 'AC Family Devices
54AC Symbol Parameter VCC (V) TA = -55°C to +125°C Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 (Note 2) VIN = VIL or VIH 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 2.4 3.7 4.7 0.1 0.1 0.1 (Note 2) VIN = VIL or VIH V V IOH -12 mA -24 mA -24 mA IOUT = 50 µA V IOUT = -50 µA V VOUT = 0.1V or VCC - 0.1V V VOUT = 0.1V or VCC - 0.1V Units Conditions
3
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54AC74/54ACT74
DC Characteristics for 'AC Family Devices
Symbol Parameter VCC (V)
(Continued)
54AC TA = -55°C to +125°C Guaranteed Limits 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input Leakage Current (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25°C is identical to 74AC @ 25°C.
Units
Conditions
0.5 0.5 0.5 V µA mA mA µA IOL
12 mA 24 mA 24 mA VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
5.5 5.5 5.5 5.5
± 1.0
50 -50 40.0
DC Characteristics for 'ACT Family Devices
54ACT Symbol Parameter VCC (V) TA = -55°C to +125°C Guaranteed Limits VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 2.0 2.0 0.8 0.8 4.4 5.4 (Note 5) VIN = VIL or VIH 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 3.70 4.70 0.1 0.1 (Note 5) VIN = VIL or VIH 4.5 5.5 IIN ICCT IOLD IOHD Maximum Input Leakage Current Maximum ICC/Input (Note 6) Minimum Dynamic Output Current 5.5 5.5 50 -50 mA mA VOLD = 1.65V Max VOHD = 3.85V Min 5.5 1.6 mA VI = VCC - 2.1V 5.5 0.50 0.50 V µA IOL 24 mA 24 mA VI = VCC, GND V V IOH -24 mA -24 mA IOUT = 50 µA V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA Units Conditions
VIL
VOH
± 1.0
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4
54AC74/54ACT74
DC Characteristics for 'ACT Family Devices
Symbol Parameter VCC (V) TA =
(Continued)
54ACT Units Conditions -55°C to +125°C Guaranteed Limits ICC Maximum Quiescent Supply Current
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25°C is identical to 74ACT @ 25°C.
5.5
40.0
µA
VIN = VCC or GND
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 8) Min fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CDn or SDn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Propagation Delay CPn to Qn or Qn Propagation Delay CPn to Qn or Qn
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V
54AC TA = -55°C to +125°C CL = 50 pF Max MHz 13.0 9.5 14.0 10.5 17.5 12.0 13.5 10.0 ns ns ns ns 70 95 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Units Fig. No.
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
AC Operating Requirements
54AC Symbol Parameter VCC (V) (Note 9) ts th tw trec Set-up Time, HIGH or LOW Dn to CPn Hold Time, HIGH or LOW Dn to CPn CPn or CDn or SDn Pulse Width Recovery Time CDn or SDn to CP
Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V
TA = -55°C to +125°C CL = 50 pF Guaranteed Limits 5.0 4.0 0.5 0.5 8.0 5.5 0.5 0.5
Units
Fig. No.
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
ns ns ns ns
5
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