|
|
Part: 5962-9161001MLA
Category:
Logic
-> Military/Aerospace->FACT ACT
Description: 54ACT823 - 9-Bit D Flip-Flop, Package: Cerdip, Pin Nb=24
Company: National Semiconductor Corporation
Datasheet: Download 5962-9161001MLA datasheet File size : 456 kB
Request For quote: Find where to buy 5962-9161001MLA
Datasheet text preview:
54ACT823 9-Bit D Flip-Flop
August 1998
54ACT823 9-Bit D Flip-Flop
General Description
The ACT823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACT823 offers noninverting outputs and is fully compatible with AMD's Am29823. n n n n TRI-STATE outputs for bus interfacing Inputs and outputs are on opposite sides ACT823 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 5962-9161001
Features
n Outputs source/sink 24 mA
Ordering Code
Order Number 54ACT823DMQB 54ACT823FMQB 54ACT823LMQB Package Number J24A W24C E28A 24-Lead Cerpack 28-Lead Ceramic Leadless Chip Carrier, Type C IEEE/IEC Package Description 24-Lead Ceramic Dual-in-line
Logic Symbols
DS100253-1
DS100253-2
Pin Names D0 D8 O0 O8 OE CLR CP EN
Description Data Inputs Data Outputs Output Enable Clear Clock Input Clock Enable
FACTTM is a trademark of Fairchild Semiconductor Corporation. TRI-STATETM is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100253
www.national.com
Connection Diagrams
Pin Assignment for DIP and Cerpack
DS100253-3
Pin Assignment for LCC
DS100253-4
www.national.com
2
Functional Description
The ACT823 consists of nine D-type edge-triggered flip-flops. These have TRI-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
Inputs OE H H H L H L H H L L CLR X X L L H H H H H H EN L L X X H H L L L L CP N N X X X X N N N N D L H X X X X L H L H Internal Q L H L L NC NC L H L H Output O Z Z Z L Z NC Z Z L H High Z High Z Clear Clear Hold Hold Load Load Load Load Function
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change
Logic Diagram
DS100253-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) -0.5V to 7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Junction Temperature (TJ) CDIP
175°C
Recommended Operating Conditions
Supply Voltage (VCC) ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
± 50 mA ± 50 mA -65°C to +150°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH VIL VOH VOL IIN IOZ ICCT IOLD IOHD ICC Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC/Input (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
VCC (V) 4.5 5.5 4.5 4.5 4.5 4.5
TA = -55°C to +125°C 2.0 2.0 0.8 0.8 3.7 0.5
Units V V
Conditions VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V IOH = -24 mA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC -2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
V V µA µA mA mA mA µA
5.5 5.5 5.5 5.5 5.5 5.5
± 1.0 ± 10.0
1.6 50 -50 160
AC Electrical Characteristics
Symbol Parameter VCC (V) (Note 4) 5.0 5.0 95 1.0 12.0 TA = -55°C to +125°C CL = 50 pF Min fmax tPLH Maximum Clock Frequency Propagation Delay CP to On ns Max MHz Units
www.national.com
4
AC Electrical Characteristics
Symbol Parameter
(Continued) VCC (V) (Note 4) 5.0 5.0 5.0 5.0 5.0 5.0 TA = -55°C to +125°C CL = 50 pF Min Max 12.0 18.0 11.5 12.0 13.5 12.0 ns ns ns ns ns ns Units
tPHL tPHL tPZH tPZL tPHZ tPLZ
Propagation Delay CP to On Propagation Delay CLR to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On
1.0 1.0 1.0 1.0 1.0 1.0
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
Symbol Parameter VCC(V) (Note 5) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 TA = -55°C to +125°C CL = 50 pF Guaranteed Minimum ts th ts th tw tw trec Setup Time, HIGH or LOW D to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW EN to CP Hold Time, HIGH or LOW EN to CP CP Pulse Width HIGH or LOW CLR Pulse Width, LOW CLR to CP Recovery Time
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
Units
4.0 3.0 4.0 3.0 6.0 7.5 4.5
ns ns ns ns ns ns ns
5
www.national.com
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
|
|
|
