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Part: 5962-9161101MKA
Category:
Logic
-> Military/Aerospace->FACT ACT
Description: 54ACT825 - 8-Bit D-type Flip-Flop, Package: Cerpack, Pin Nb=24
Company: National Semiconductor Corporation
Datasheet: Download 5962-9161101MKA datasheet File size : 456 kB
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54ACT825 8-Bit D Flip-Flop
February 1999
54ACT825 8-Bit D Flip-Flop
General Description
The 'ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multi-use control of the interface. The 'ACT825 has noninverting outputs and is fully compatible with AMD's Am29825.
Features
n n n n Outputs source/sink 24 mA Inputs and outputs are on opposite sides 'ACT825 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) -- 'ACT825: 5962-91611
Logic Symbols
IEEE/IEC
DS100254-1
DS100254-3
Pin Names D0 D7 O0 O7 OE1, OE2, OE3 EN CLR CP
Description Data Inputs Data Outputs Output Enables Clock Enable Clear Clock Input
FACTTM is a trademark of Fairchild Semiconductor. TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100254
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Connection Diagrams
Pin Assignment for DIP and Flatpak Pin Assignment for LCC
DS100254-4 DS100254-2
Functional Description
The 'ACT825 consists of eight D-type edge-triggered flip-flops. These devices have TRI-STATE ® outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The 'ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
Inputs OE H H H L H L H H L L CLR X X L L H H H H H H EN L L X X H H L L L L CP
N N
Internal Dn L H X X X X L H L H Q L H L L NC NC L H L H
Output O Z Z Z L Z NC Z Z L H
Function High-Z High-Z Clear Clear Hold Hold Load Load Load Load
X X X X
N N N N
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change
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2
Logic Diagram
DS100254-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) -0.5V to 7.0V -20 mA +20 mA -0.5V to VCC +0.5V -20 mA +20 mA +0.5V
Junction Temperature (TJ) CDIP
175°C
Recommended Operating Conditions
Supply Voltage (VCC) 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC -55°C to +125°C
± 50 mA ± 50 mA -65°C to +150°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics
Symbol Parameter VCC (V) 54ACT TA = -55°C to +125°C Guaranteed Limits VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level 4.5 5.5 4.5 5.5 4.5 5.5 2.0 2.0 0.8 0.8 4.4 5.4 (Note 2) VIN = VIL or VIH IOH = -24 mA IOH = -24 mA IOUT = 50 µA (Note 2) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC -2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V V VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V IOUT = -50 µA Units Conditions
4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5
3.70 4.70 0.1 0.1
V V
4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC/Input (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
0.50 0.50
V µA µA mA mA mA µA
5.5 5.5 5.5 5.5 5.5 5.5
± 1.0 ± 10.0
1.6 50 -50 160
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DC Electrical Characteristics
(Continued)
Note 4: ICC limit for 54ACT @ 25°C is identical to 74ACT @ 25°C.
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 5) Min fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Propagation Delay CLR to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V
54ACT TA = -55°C to +125°C CL = 50 pF Max MHz 11.5 11.5 18.0 11.5 12.5 13.5 13.0 ns ns ns ns ns ns ns 95 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Units
Fig. No.
5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
AC Operating Requirements
VCC Symbol Parameter (V) (Note 6) 54ACT TA = -55°C to +125°C CL = 50 pF Guaranteed Minimum ts th ts th tw tw trec Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW EN to CP Hold Time, HIGH or LOW EN to CP CP Pulse Width HIGH or LOW CLR Pulse Width, LOW CLR to CP Recovery Time
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V
Fig. Units No.
5.0 5.0 5.0 5.0 5.0 5.0 5.0
4.0 2.5 4.0 2.0 6.0 7.0 4.5
ns ns ns ns ns ns ns
5
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