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Part: 5962-9165401VXA
Category:
Logic
-> Military/Aerospace->ECL
Description: 100355 - Low Power Quad Multiplexer/Latch, Package: Cerdip, Pin Nb=24
Company: National Semiconductor Corporation
Datasheet: Download 5962-9165401VXA datasheet File size : 456 kB
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100355 Low Power Quad Multiplexer/Latch
August 1998
100355 Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or D1, the Select inputs can force the outputs LOW for the case where the latch is transparent (both Enables are LOW) and can steer a HIGH signal from either D0 or D1 to an output. The Select inputs can be tied together for applications requiring only that data be steered from either D0 or D1. A positive-going signal on either Enable input latches the outputs. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and forces the Q outputs LOW. All inputs have 50 k pulldown resistors.
Features
n n n n n Greater than 40% power reduction of the 100155 2000V ESD protection Pin/function compatible with 100155 Voltage compensated operating range = -4.2V to -5.7V Standard Microcircuit Drawing (SMD) 5962-9165401
Logic Symbol
DS100294-1
Pin Names E1, E2 S0, S1 MR Dna Dnd Qa Qd Qa Qd
Description Enable Inputs (Active LOW) Select Inputs Master Reset Data Inputs Data Outputs Complementary Data Outputs
Connection Diagrams
24-Pin DIP 24-Pin Quad Cerpak
DS100294-3
DS100294-2
© 1998 National Semiconductor Corporation
DS100294
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Logic Diagram
DS100294-5
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Operating Mode Table
Controls E1 H X L L L L E2 X H L L L L S1 X X L H L H S0 X X L L H H Outputs Qn Latched (Note 1) Latched (Note 1) D0x D0x + D1x L D1x
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Note 1: Stores data present before E went HIGH
Truth Table
Inputs MR H L L L L L L L L L L E1 X L L L L L L L L H X E2 X L L L L L L L L X H S1 X H H L L L H H H X X S0 X H H L L H L L L X X D1x X H L X X X H X L X X D0x X X X H L X X H L X X Qx H L H L H H L L H Outputs Qx L H L H L L H H L
Latched (Note 1) Latched (Note 1)
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Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired. Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) -65°C to +150°C +175°C -7.0V to +0.5V VEE to +0.5V -50 mA
ESD (Note 3)
2000V
Recommended Operating Conditions
Case Temperature (TC) Military Supply Voltage (VEE) -55°C to +125°C -5.7V to -4.2V
Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version DC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -55°C to +125°C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current S0, S1 E1, E2 Dna Dnd MR S0, S1 E1, E2 Dna Dnd MR IEE Power Supply Current -95 220 350 340 430 320 500 490 630 -32 mA -55°C to +125°C Inputs Open (Notes 4, 5, 6) µA -55°C µA 0°C to +125°C VEE = -5.7V VIN = VIH (Max) (Notes 4, 5, 6) -1165 Min -1025 -1085 Max -870 -870 Units mV mV mV mV mV mV -1610 -1555 -870 mV mV mV mV µA TC 0°C to +125°C -55°C 0°C to +125°C -55°C 0°C to +125°C -55°C 0°C to +125°C -55°C -55°C to +125°C -1830 -1475 0.50 -55°C to +125°C -55°C to +125°C Guaranteed HIGH Signal for ALL Inputs Guaranteed LOW Signal for ALL Inputs VEE = -4.2V VIN = VIL
(Min)
Conditions VIN = VIH Loading with 50 to -2.0V
Notes (Notes 4, 5, 6)
(Max)
-1830 -1620 -1830 -1555 -1035 -1085
or VIL (Min)
VIN = VIH
(Min)
Loading with 50 to -2.0V
or VIL (Max)
(Notes 4, 5, 6) (Notes 4, 5, 6, 7) (Notes 4, 5, 6, 7) (Notes 4, 5, 6)
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 5: Screen tested 100% on each device at -55°C, +25°C, and +125°C Temp., Subgroups 1, 2, 3, 7, and 8. Note 6: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25°, +125°C, and -55°C Temp., Subgroups 1, 2, 3, 7, and 8. Note 7: Guaranteed by applying specified input condition and testing VOH/VOL.
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Military Version AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dna Dnd S0, S1 MR (Release Time) tH Hold Time Dna Dnd S0, S1 tpw (L) tpw (H) Pulse Width LOW E1, E2 Pulse Width HIGH MR 0.40 0.00 2.00 2.00 0.40 0.00 2.00 2.00 0.40 0.00 2.00 2.00 ns ns ns 0.90 2.40 1.50 0.90 2.40 1.50 0.90 2.40 1.50 ns 0.40 1.90 0.40 1.90 0.40 1.90 ns 0.60 2.80 0.70 2.60 0.70 2.90 ns 0.50 2.60 0.60 2.30 0.70 2.70 ns 0.60 3.00 0.80 2.70 0.80 3.20 ns 0.40 2.30 0.50 2.20 0.50 2.60 ns TC = -55°C Min Max TC = +25°C Min Max TC = +125°C Min Max Units Conditions Notes
Figures 1, 2
(Notes 8, 9, 10)
Figures 1, 3 Figures 1, 2
(Notes 8, 9, 10) (Note 11)
Figure 4 Figure 3 Figure 4 Figure 2 Figure 3
(Note 11)
(Note 11) (Note 11) (Note 11)
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 9: Screen tested 100% on each device at +25°C, Temperature only, Subgroup A9. Note 10: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25°, Subgroup A9, and at +125°C, and -55°C Temp., Subgroups A10 & A11. Note 11: Not tested at +25°C, +125°C and -55°C Temperature (design characterization data).
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