|
|
Part: 5962-9475001QYA
Category:
Logic
-> Military/Aerospace->MILSCAN
Description: SCANPSC100F - Embedded Boundary Scan Controller, Package: Cerdip, Pin Nb=28
Company: National Semiconductor Corporation
Datasheet: Download 5962-9475001QYA datasheet File size : 493 kB
Request For quote: Find where to buy 5962-9475001QYA
Datasheet text preview:
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support)
September 1998
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support)
General Description
The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The 'PSC100F operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Scan data returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the 'PSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the 'PSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the number of TCK cycles required to complete a scan operation within the boundary scan chain or to complete a 'PSC100F Built-In Self Test (BIST) operation. SCANPSC100F device drivers and 1149.1 embedded test application code are available with National's SCANEase software tools.
Features
n Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture n Supported by National's SCAN Ease (Embedded Application Software Enabler) Software n Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies n Directly supports up to two 1149.1 scan chains n 16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) port n Automatically produces pseudo-random patterns at the Test Data Out (TDO) port n Fabricated on FACTTM 1.5 µm CMOS process n Supports 1149.1 test clock (TCK) frequencies up to 25 MHz n TTL-compatible inputs; full-swing CMOS outputs with 24 mA source/sink capability n Standard Microcircuit Drawing (SMD) 5962-9475001
Connection Diagrams
28-Pin DIP and Flatpak Pin Assignment for LCC
10032518
10032501
FACTTM is a trademark of Fairchild Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation
DS100325
www.national.com
SCANPSC100F Embedded
Chip Architecture
The 'PSC100 is designed to act together with a parallel bus host as a serial test bus master. Parallel data is written by the host to the 'PSC100, which serializes the data for application to a serial test bus. Serial data returning from the target scan chain(s) is placed on the processor port for parallel reads. Several features are included in the 'PSC100 which make scan test communication more convenient and efficient. ceives serial data from the scan chain. A local control block is associated with each Shifter/Buffer to provide shift and load control as well as providing full or empty status. The SSI also provides Test Clock (TCK) Control. TCK is stopped and started depending on the status of the Shifter/Buffers or the 32-bit Counter. By stopping and starting TCK, scan operations will proceed only when the enabled Shifter/Buffers are ready to send and/or receive serial data. The 32-bit Counter (CNT32) is a count-down binary counter included to assist in controlling the SSI. The initial state of CNT32 is loaded from the parallel port with four consecutive writes to its address. When enabled, CNT32 is used to program the number of TCKs applied by the SSI to the boundary scan chain(s). The value of CNT32 can also be used to generate interrupts (i.e., when CNT32 reaches terminal count) and to trigger 'PSC100 features, such as, Auto TMS High (discussed later within this datasheet). The Mode and Status Registers are used to control and observe the operation of the SSI and CNT32. Each of the Shifter/Buffers and CNT32 have an associated mode bit which enables it for participation in on-going operations. Status bits can be used for polling operations.
Figure 1 shows the major functional blocks of the 'PSC100 design. The Parallel Processor Interface (PPI) is an asynchronous, 8-bit parallel interface which is used by the host processor to write and read data. The PPI generates the necessary internal data, address, and control signals to complete internal write and read operations. The Serial Scan Interface (SSI) consists of a bank of double-buffered parallel/serial shift registers (i.e., a 2 x 8 bit FIFO), or Shifter/Buffers. The double buffering improves efficiency by allowing parallel writes or reads to/from one of the two 8-bit FIFOs within the shifter/buffer while the other FIFO is shifting data to/from the scan chain. Three Shifter/Buffers are provided for outgoing serial data and one for incoming serial data. Test Data Out (TDO) is for scanning out test data while the two Test Mode Select signals (TMS0/1) are used to provide user specific control data. Test Data In (TDI) re-
10032502
FIGURE 1. 'PSC100 Block Diagram
www.national.com
2
SCANPSC100F Embedded
Pin Descriptions
Pin Name RST (Input) The Reset pin is an asynchronous input that, when low, initializes the 'PSC100. Mode bits, Shifter/Buffer and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis for improved noise immunity. The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK. SCK has hysteresis for improved immunity. Output Enable TRI-STATEs all SSI outputs when high. A 20 k pull-up resistor is connected to automatically TRI-STATE ® these outputs when this signal is floating. Chip Enable, when low, enables the PPI for byte transfers. D(7:0) and RDY are TRI-STATEd if CE is high. CE has hysteresis for improved noise immunity. Read/Write defines a PPI cycle -- Read when high, Write when low. R/ W has hysteresis for improved noise immunity. Strobe is used for timing all PPI byte transfers. D(7:0) are TRI-STATEd when STB is high. All other PPI inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for improved noise immunity. The Address pins are used to select the register to be written to or read from. Bidirectional pins used to transfer parallel data to and from the 'PSC100. Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active high. Ready is used to synchronize asynchronous byte transfers between the host and the 'PSC100. When low, RDY signals that the addressed register is ready to be accessed RDY is enabled when CE is low. Test Data Out is the serial scan output from the 'PSC100. TDO is enabled when OE is low. Description
SCK (Input) OE (Input) CE (Input) R/W (Input) STB (Input)
A(2:0) (Input) D(7:0) (I/O) INT (Output) RDY (TRI-STATE Output) TDO (TRI-STATE Output) TMS(1:0) (TRI-STATE Output) TCK (TRI-STATE Output) TDI (Input) FRZ (Input)
The Test Mode Select pins are serial outputs used to supply control logic to the UUT. TMS(1:0) are enabled when OE is low. The Test Clock output is a buffered version of SCK for distribution in the UUT. TCK Control logic starts and stops TCK to prevent overflow and underflow conditions. TCK is enabled when OE is low. Test Data In is the serial scan input to the 'PSC100. A 20 k pull-up resistor is connected to force TDI to a logic 1 when the TDO line from the UUT is floating. The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode bit is set, TCK will be forced high if FRZ goes high. FRZ has hysteresis for improved noise immunity.
3
www.national.com
SCANPSC100F Embedded
Mode and Status Registers MODE REGISTER 0 (MODE0)
Bit 7 TDO Enable Bit 6 TDI Enable Bit 5 CNT32 Enable Bit 4 TMS0 Enable Bit 3 TMS1 Enable Reserved Bit 2 Bit 1 Auto TMS High Enable Bit 0 LoopAround Enable This register is purely a mode register. All bits are writeable and readable. The value 00100000 is placed in this register upon RST low or a synchronous reset operation. · Bit 7: This bit enables the TDO shifter/buffer for shift operations. If this bit is set, the TDO shifter/buffer will cause TCK to stop if it is empty.
· Bit 6: This bit enables the TDI shifter/buffer for shift operations. If this bit is set, the TDI shifter/buffer will cause TCK to stop if it is full. · Bit 5: This bit enables the 32-bit counter. If this bit is set, the counter will cause TCK to stop if if has not been loaded or if it has reached terminal count.
www.national.com
4
SCANPSC100F Embedded
Mode and Status Registers
(Continued)
· Bit 4: This bit enables the TMS0 shifter/buffer for shift operations. If this bit is set, the TMS0 shifter/buffer will cause TCK to stop if it is empty. · Bit 3: This bit enables the TMS1 shifter/buffer for shift operations. If this bit is set, the TMS1 shifter/buffer will cause TCK to stop if it is empty. · Bit 2: This bit is reserved and should remain as a logic 0 during all 'PSC100 operations. · Bit 1: If this bit is set, TMS will be forced high when the 32-bit counter is at state (00000001)h. · Bit 0: This bit causes TDI to be connected directly back through TDO for Loop-Around operations.
MODE REGISTER 1 (MODE1)
Bit 7 TDO Interrupt Enable Bit 6 TDI Interrrupt Enable Bit 5 CNT32 Interrupt Enable Bit 4 PRPG Enable Bit 3 SSC Enable Bit 2 Freeze Pin Enable Bit 1 Test LoopBack Bit 0 Test LoopBack
This register is purely a mode register. All bits are writeable and readable. The value 00000000 is placed in this register upon RST low or a synchronous reset operation. If this bit is set and the TDO shifter/buffer is not full (i.e., one or both 8-bit TDO FIFOs are empty), the INT pin will · Bit 7: go high.
· Bit 6: · Bit 5: · Bit 4:
If this bit is set and the TDI shifter/buffer is not empty (i.e., one or both 8-bit TDI FIFOs are full), the INT pin will go high. If this bit is set, and the 32-bit counter is not loaded or has reached terminal count, the INT pin will go high. This bit signifies that the TD0 shifter/buffer is reconfigured as a 32-Bit Pseudo Random Pattern Generator. If set, and MODE0 Bit 7 is set, the TDO shifter/buffer will stop TCK until a seed value has been written to all four of the 8-bit LFSR segments. This bit signifies that the TD1 shifter/buffer is reconfigured as a 16-Bit Serial Signature Compactor. If set, and MODE0 Bit 6 is set, the TDI shifter/buffer will cause TCK to stop until a seed value has been written to the two TDI registers.
· Bit 3:
If this bit is set, a high value on FRZ will force TCK high (see TCK Control Section). · Bit 2: · Bits 1 and 0: These bits are used to control Test Loop-Back operations according to the following table. MODE1 Bit 1 0 0 MODE1 Bit 0 0 1 Normal Operation Loop-Back TDO to TDI Function MODE1 Bit 1 1 1 MODE1 Bit 0 0 1 Loop-Back TMS0 to TDI Loop Back TMS1 to TDI Function
MODE REGISTER 2 (MODE2) Write: Bit 7 Not Used Bit 6 Not Used Bit 5 Not Used Bit 4 Not Used Bit 3 Continuous Update Bit 2 Update Status Reset Bit 1 Bit 0 Single Step CNT32 Read: Bit 7 TDO Status Bit 6 TDI Status Bit 5 CNT32 Status Bit 4 TMS0 Status Bit 3 TMS1 Status Bit 2 Continuous Update Reset Bit 1 Bit 0 Single Step CNT32 This register contains both mode and status bits. Bits 4 7 are status bits only. Bit 3 is a status bit during read operations and a mode bit during write operations. Bits 0 2 are mode bits only. Upon RST low, or a synchronous reset, the value placed in MODE2 is 10111000 (Read mode). Latches used to update status bits 3 7 retain their last state upon RST and are in an "unknown" state after power-up. To initialize the latches to a known state, they need to be updated using the Update Status bit (bit 2) or continuous update bit (bit 3). · Bit 7: Set high if the TDO shifter/buffer is not full, i.e., one or both 8-bit TDO FIFOs are ready to be written to.
· Bit 6: Set high if the TDI shifter/buffer is not empty, i.e., one or both 8-bit TDI FIFOs are ready to be read from.
5
www.national.com
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
|
|
|
