Details, datasheet, quote on part number: 5962F7802302VFA
CategoryInterface and Interconnect => RS-422/RS-423
DescriptionDS26F31M - Quad High Speed Differential Line Drivers, Package: Lcc, Pin Nb=20
CompanyNational Semiconductor Corporation
DatasheetDownload 5962F7802302VFA datasheet
Cross ref.Similar parts: DS26F31MW-QMLV, DS26F31MW/883, DS26F31MWFQMLV, 5962-7802302MFA, 5962F7802302VFX, AM26C31M, AM26LS31M, DS26C31MQML, DS26LS31MQML
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Features, Applications

DS26F31M Quad High Speed Differential Line Drivers

The is a quad differential line driver designed for digital data transmission over balanced lines. The DS26F31 meets all the requirements of EIA Standard RS-422 and Federal Standard It is designed to provide unipolar differential drive to twisted-pair or parallel-wire transmission lines. The DS26F31 offers improved performance due to the use of state-of-the-art L-FAST bipolar technology. The L-FAST technology allows for higher speeds and lower currents by utilizing extremely short gate delay times. Thus, the DS26F31 features lower power, extended temperature range, and improved specifications. The circuit provides an enable and disable function common to all four drivers. The DS26F31M features TRI-STATE outputs and logical OR-ed complementary enable inputs. The inputs are all LS compatible and are all one unit load. The DS26F31M offers optimum performance when used with the DS26F32 Quad Differential Line Receiver.


Military temperature range Output skew 2.0 ns typical Input to output delay 10 ns Operation from single +5.0V supply 16-lead ceramic DIP Package Outputs won't load line when VCC = 0V Output short circuit protection Meets the requirements of EIA standard RS-422 High output drive capability for 100 terminated transmission lines

FIGURE 1. Logic Symbol 20-Lead Ceramic Leadless Chip Carrier (E)

Top View For Complete Military Product Specifications, refer to the appropriate SMD or MDS. Order Number or DS26F31MW/883 See NS Package Numbers or W16A

TRI-STATE is a registered trademark of National Semiconductor Corporation.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Ceramic DIP to +175C Lead Temperature Ceramic DIP (Soldering, 60 sec.) 300C Maximum Power (Note 1) Dissipation at 25C Cavity Package 1500 mW

Supply Voltage Input Voltage Output Voltage
Note 1: Derate cavity package 10 mW/C above 25C.

over operating range, unless otherwise specified Symbol VOH VOL VIH VIL IIL IIH IIR IOZ VIC IOS ICCX ICC tPLH tPHL SKEW tLZ tHZ tZL tZH Input to Output Input to Output to Output Enable to Output Enable to Output Enable to Output Enable to Output Parameter Output Voltage HIGH Output Voltage LOW Input Voltage HIGH Input Voltage LOW Input Current LOW Input Current HIGH Input Reverse Current Off State (High Impedance) Output Current Input Clamp Voltage Output Short Circuit Supply Current

Conditions = Min, IOH mA = Min, IOL mA = Min = Max = Max, 0.4V = Max, 2.7V = Max, = 0.5V
= Min, mA = Max (Note 5) = Max, All Outputs Disabled = Max, All Outputs Enabled = 25C,
Load = (Notes = 25C, Load = (Note = 25C, Load = (Notes pF V

Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation. Note 3: Unless otherwise specified min/max limits apply across the to +125C temperature range for the DS26F31M and across the OC to +70C range for the DS26F31C. All typicals are given for = 5V and = 25C. Note 4: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 5: Only one output at a time should be shorted. Note = 30 pF, = 1.3V, VPULSE to +3V (See AC Load Test Circuit for TRI-STATE Outputs). Note 7: Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.

FIGURE 2. AC Load Test Circuit for TRI-STATE Outputs

Note 8: Diagram shown for Enable Low. Switches S1 and S2 open. Note 9: S1 and S2 of Load Circuit are closed except where shown. Note 10: Pulse Generator for all Pulses: Rate 1.0 MHz, tr 6.0 ns, tf 6.0 ns. Note 11: CL includes probe and jig capacitance.


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