|Category||Logic => Registers => Bipolar->F Family|
|Description||Quad 2-port Register|
|Company||National Semiconductor Corporation|
|Datasheet||Download 74F398 datasheet
The 'F398 and 'F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops A common Select input determines which of the two 4-bit words is accepted The selected data enters the flipflops on the rising edge of the clock The 'F399 is the 16-pin version of the 'F398 with only the Q outputs of the flip-flops availableFeatures
Select inputs from two data sources Fully positive edge-triggered operation Both true and complement outputs 'F398 Guaranteed 4000V minimum ESD protection 'F399
Package Description (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
54F398DM (Note 2) 74F398SC (Note 1) 54F398FM (Note 2) 54F398LM (Note 74F399PC 54F399DM (Note 2) 74F399SC (Note 1) 74F399SJ (Note 1) 54F399FM (Note 2) 54F399LM (Note 2)
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation
Common Select Input Clock Pulse Input (Active Rising Edge) Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs Register Complementary Outputs ('F398)
The 'F398 and 'F399 are high-speed quad 2-port registers They select four bits of data from either of two sources (Ports) under control of a common Select input (S) The selected data is transferred a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP) The 4-bit D-type output register is fully edge-triggered The Data inputs (I0x I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation The 'F398 has both Q and Q outputs Inputs I0
H e HIGH Voltage Level L e LOW Voltage Level h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X e Immaterial 'F398 only
'F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
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