|Category||Logic => Latches => Bipolar->F Family|
|Description||Octal D-type Latch With Tri-state Outputs|
|Company||National Semiconductor Corporation|
|Datasheet||Download 74F563 datasheet
|54F 74F563 Octal D-Type Latch with TRI-STATE Outputs
The is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs This device is functionally identical to the 'F573 but has inverted outputsFeatures
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to 'F573
Package Description (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line (0 300 Wide) Molded Small Outline JEDEC (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation 9562 RRD-B30M75 Printed S A
The 'F563 contains eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Inputs OE LEFunction Table Internal L NC Output NC High Z High Z High Z Latched Transparent Latched Function
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance e No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max)Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial
Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs
Symbol VIH VIL VCD VOH Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC 54F 10% VCC 74F 10% VCC 54F 74FConditions Recognized as a HIGH Signal Recognized as a LOW Signal
VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCL ICCZ
Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current
IOL 20 mA IOL 24 mA VIN 2 7V VIN 7 0V VOUT e VCC IID 9 mA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN 0 5V VOUT 2 7V VOUT 0 5V VOUT e 0V VOUT VO e LOW VO e HIGH Z
Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current 40 3
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