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Details, datasheet, quote on part number:93L00FMQB
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Datasheet text preview:
93L00 4-Bit Universal Shift Register
June 1989
93L00 4-Bit Universal Shift Register
General Description
The 93L00 is a 4-bit universal shift register As a high speed multifunctional sequential logic block it is useful in a wide variety of register and counter applications It may be used in serial-serial shift left shift right serial-parallel parallelserial and parallel-parallel data register transfers
Y Y
eatures
Asynchronous master reset J K inputs to first stage
F
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 9576 2
VCC e Pin 16 GND e Pin 8
TL F 9576 1
Order Number 93L00DMQB or 93L00FMQB See NS Package Number J16A or W16A
Pin Names PE P0 P3 J K CP MR Q0 Q3 Q3
Description Parallel Enable Input (Active LOW) Parallel Inputs First Stage J Input (Active HIGH) First Stage K Input (Active LOW) Clock Pulse Input (Active Rising Edge) Master Reset Input Parallel Outputs Complementary Last Stage Output
C1995 National Semiconductor Corporation
TL F 9576
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note) Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings T he ``Recommended Operating Conditions'' table will define the conditions for actual device operation
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage Input Voltage 7V 5 5V
Operating Free Air Temperature Range R b 65 C to a 125 C MIL
ecommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) tw (H) tw (L) tw (L) trec Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW J K and P0 P3 to CP Hold Time HIGH or LOW J K and P0 P3 to CP Setup Time HIGH or LOW PE to CP Hold Time HIGH or LOW PE to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP
b 55
93L00 (MIL) Nom 5 Max 55
Units V V 07
b0 4
45 2
V mA mA
48 125
C
ns ns ns ns ns ns ns
60 60 0 0 68 68 0 0 38 38 53 70
2
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage
Max
Conditions VCC e Min II e b10 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V Inputs CP PE
Min
Typ (Note 1)
Max
b1 5
Units V V
2
4
34 0 3
V mA
1 20 40 46
b 400 b 800 b 920 b2 5 b 25
High Level Input Current
mA
IIL
Low Level Input Current
VCC e Max VI e 0 3V
Inputs CP PE
mA
IOS ICC
Short Circuit Output Current Supply Current
VCC e Max (Note 2) VCC e Max
mA mA
23
Note 1 All typicals are at VCC e 5V TA e 25 C S te 2 Not more than one output should be shorted at a time and the duration should not exceed one second o
witching Characteristics
VCC e a 5 0V TA e a 25 C (See Section 1 for waveforms and load configurations) 93L Symbol Parameter Min fmax tPLH tPHL tPHL Maximum Shift Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn 10 35 51 60 CL e 15 pF Max MHz ns ns Units
3
Functional Description
The Logic Diagrams and Truth Table indicate the functional characteristics of the 93L00 4-bit shift register The device is useful in a wide variety of shifting counting and storage applications It performs serial parallel serial-to-parallel or T parallel-to-serial data transfers he 93L00 has two primary modes of operation shift right (Q0 x Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input When the PE input is HIGH serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 x Q1 x Q2 x Q3 following each LOW-to-HIGH clock transition The JK inputs provide the flexibility of the JK type input for special applications and the simple D-type T input for general applications by tying the two pins together hen the PE input is LOW the 93L00 appears as four common clocked D flip-flops The data on the parallel inputs P0 P3 is transferred to the respective Q0 Q3 outputs following the LOW-to-HIGH clock transition Shift left operation (Q3 x Q2) can be achieved by tying the Qn outputs to th A e Pnb1 inputs and holding the PE input LOW ll serial and parallel data transfers are synchronous occuring after each LOW-to-HIGH clock transition Since the 93L00 utilizes edge triggering there is no restriction on the activity of the J K Pn and PE inputs for logic operation except for the setup and release time requirements A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW independent of any other input condition W
ruth Table
Operating Mode Inputs (MR e H) PE H H H H L L J L L H H X X K L H L H X X P0 X X X X L H P1 X X X X L H P2 X X X X L H P3 X X X X L H Q0 L Q0 Q0 H L H Q1 Q0 Q0 Q0 Q0 L H Outputs Q2 Q1 Q1 Q1 Q1 L H
ta n1
Q3 Q2 Q2 Q2 Q2 L H
Q3 Q2 Q2 Q2 Q2 H L
Shift Mode
Parallel Entry Mode
H a 1 e Indicates state after next LOW-to-HIGH clock transition tn e HIGH Voltage Level L e LOW Voltage Level X e Immaterial
4
Logic Diagram
TL F 9576 3
5
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