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Details, datasheet, quote on part number:93L28FMQB
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Datasheet text preview:
93L28 Dual 8-Bit Shift Register
June 1989
93L28 Dual 8-Bit Shift Register
General Description
The 93L28 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers The multifunctional capability of this device is provided by several features 1) additional gating is provided at the input to both shift registers so that the input is easily multiplexed between two sources 2) the clock of each register may be provided separately or together 3) both the true and coma plementary outputs are provided from each 8-bit register nd both registers may be master cleared from a common input
Y Y Y
eatures
2-input multiplexer provided at data input of each register Gated clock input circuitry Both true and complementary outputs provided from last bit of each register Asynchronous master reset common to both registers
Y
F
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10200 1
Order Number 93L28DMQB or 93L28FMQB See NS Package Number J16A or W16A
TL F 10200 2
VCC e Pin 16 GND e Pin 8
Pin Names S D0 D1 CP
Description Data Select Input Data Inputs Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) Master Reset Input (Active LOW) Last Stage Output Complementary Output
MR Q7 Q7
C1995 National Semiconductor Corporation
TL F 10200
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage Input Voltage 7V 5 5V Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings T he ``Recommended Operating Conditions'' table will define the conditions for actual device operation
Operating Free Air Temperature Range R b 55 C to a 125 C MIL b 65 C to a 150 C Storage Temperature Range
ecommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) tw(L) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Clock Pulse Width HIGH or LOW MR Pulse Width with CP HIGH MR Pulse Width with CP LOW
b 55
93L28 (MIL) Nom 5 Max 55
Units V V 07
b 400
45 2
V mA mA
48 125
C
ns ns ns ns ns
30 30 0 0 55 55 60 70
2
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage HIGH Level Input Current
Max
Conditions VCC e Min II e b10 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V MR Dx CP (7 10) S CP Com
Min
Typ (Note 1)
Max
b1 5
Units V V
2
4 0 3
V mA
1 20 30 40 60
b 400 b 600 b 800 b 1200 b2 5 b 25
mA
IIL
LOW Level Input Current
VCC e Max VI e 0 3V
MR Dx CP (7 10) S CP Com
mA
IOS ICC
Short Circuit Output Current Supply Current
VCC e Max (Note 2) VCC e Max
mA mA
25 3
Note 1 All typicals are at VCC e 5V TA e 25 C S te 2 Not more than one output should be shorted at a time and the duration should not exceed one second o
witching Characteristics
VCC e a 5 0V TA e a 25 C (See Section 1 for test waveforms and output load) Symbol fmax tPLH tPHL tPHL Parameter Min Maximum Shift Right Frequency Propagation Delay CP to Q7 or Q7 Propagation Delay MR to Q7 50 45 80 110 CL e 15 pF Max MHz ns ns Units
3
Functional Description
The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7) The clocking of each register is controlled by the OR function of the separate and the common clock input Each register is composed of eight clocked RS master slave flip-flops and a number of gates The clock OR gate drives the eight clock inputs of the flip-flops in parallel When the two clock inputs t (the separate and the common) to the OR gate are LOW he slave latches are steady but data can enter the master latches via the R and S input During the first LOW-to-HIGH transition of either or both simultaneously of the two clock inputs the data inputs (R and S) are inhibited so that a later change in input data will not affect the master then the now W trapped information in the master is transferred to the slave hen the transfer is complete both the master and the slave are steady as long as either or both clock inputs remain HIGH During the HIGH-to-LOW transition of the last remaining HIGH clock input the transfer path from master to slave is inhibited first leaving the slave steady in its present state The data inputs (R and S) are enabled so that new data can enter the master Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH signal ach 8-bit shift register has a 2-input multiplexer in front of the serial data input The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean S expression erial data in SD e SD0 a SD1 An asynchronous master reset is provided which when activated by a LOW logic level will clear all 16 stages independently of any other input signal S hift Select Table Inputs S L L H H D0 L H X X D1 X X L H Output Q7 (tn a 8) L H L H
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial E n a 8 e Indicates state after eight clock pulse
Logic Diagram
TL F 10200 3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L28DMQB NS Package Number J16A
5
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