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Details, datasheet, quote on part number:93L38
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| Part: | 93L38 |
| Category: | Logic => Registers => Bipolar->TTL Family |
| Description: | 8-bit Multiple Port Register (discontinued) |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download 93L38 datasheet File size : 131 kB |
| Request For quote: | Find where to buy 93L38
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Datasheet text preview:
93L38 8-Bit Multiple Port Register
July 1989
93L38 8-Bit Multiple Port Register
General Description
The 93L38 is an 8-bit multiple port register designed for high speed random access memory applications where the ability to simultaneously read and write is desirable A common use would be as a register bank in a three address computer Data can be written into any one of the eight bits and read from any two of the eight bits simultaneously The circuit uses TTL technology and is compatible with all TTL families
Y Y
eatures
r Master slave operation permitting simultaneous write ead without race problems Simultaneously read two bits and write one bit in any one of eight bit positions Readily expandable to allow for larger word sizes
Y
F
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10202 1
TL F 10202 2
Order Number 93L38DMQB or 93L38FMQB See NS Package Number J16A or W16A
VCC e Pin 16 GND e Pin 8
Pin Names A0 A2 DA B0 B2 C0 C2 CP SLE ZB ZC
Description Write Address Inputs Data Input B Read Address Inputs C Read Address Inputs Clock Pulse Input (Active Rising Edge) Slave Enable Input (Active LOW) B Output C Output
C1995 National Semiconductor Corporation
TL F 10202
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage Input Voltage Operating Free Air Temperature Range R Military Storage Temperature Range
b 55 b 65
7V 5 5V
C to a 125 C C to a 150 C
Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings T he ``Recommended Operating Conditions'' table will define the conditions for actual device operation
ecommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA ts (H) ts (L) th (H) th (L) ts (H) ts (L) th (H) th (L) tw (H) tw (L) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW DA to CP Hold Time HIGH or LOW DA to CP Setup Time HIGH or LOW An to CP Hold Time HIGH or LOW An to CP CP Pulse Width HIGH or LOW
b 55
93L38 (MIL) Nom 5 Max 55
Units V V 07
b 400
45 2
V mA mA
48 125
C
ns ns ns ns ns
30 22 0
b4 0
0 0 0 0 40 30
Electrical Characteristics over recommended operating free air temperature (unless othewise noted)
Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage
Max
Conditions VCC e Min II e b10 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V VCC e Max VI e 0 3V VCC e Max (Note 2) VCC e Max (Note 3)
Min
Typ (Note 1)
Max
b1 5
Units V V
2
4 03 1 50
b2
V mA mA mA mA mA
High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current
b2 5
b 25
70
Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second ote 3 ICC is measured with all outputs open and all input grounded 2
Switching Characteristics VCC e a 5 0V
Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter
TA e a 25 C (See Section 1 for Test Waveforms and Output Load CL e 15 pF Min Max 68 95 70 92 65 57 ns ns ns Units
Propagation Delay Bn or Cn or Zn Propagation Delay DA to Zn Propagation Delay CP to Zn
Functional Description
The 93L38 8-bit multiple port register can be considered a 1-bit slice of eight high speed working registers Data can be written into any one and read from any two of the eight locations simultaneously Master slave operation eliminates all race problems associated with simultaneous read write activity from the same location When the clock input (CP) is LOW data applied to the data input line (DA) enters the selected master This selection is accomplished by coding D the three write input select lines (A0 A2) appropriately ata is stored synchronously with the rising edge of the T clock pulse he information for each of the two slaved (output) latches is selected by two sets of read address inputs (B0 B2 and C0 C2) The information enters the slave while the clock is HIGH and is stored while the clock is LOW If Slave Enable is LOW (SLE) the slave latches are continuously enabled The signals are available on the output pins (ZB and ZC) he input bit selection and the two output bit selections can be accomplished independently or simultaneously The data flows into the device is demultiplexed according to the state of the write address lines and is clocked into the selected latch The eight latches function as masters and store the input data The two output latches are slaves and hold the data during the read operation The state of each slave is determined by the state of the master selected by its associT ated set of read address inputs he method of parallel expansion is shown in Figure A One T 93L38 is needed for each bit of the required word length he read and write input lines should be connected in common on all of the devices This register configuration provides two words of n-bits each at one time where n devices are connected in parallel T T
L F 10202 4
FIGURE A Parallel Expansion
3
Logic Diagram
TL F 10202 3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L38DMQB NS Package Number J16A
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