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Details, datasheet, quote on part number:ADC0803
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| Part: | ADC0803 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | ADC0803 - 8-Bit µP Compatible A/D Converters, Package: Mdip, Pin Nb=20 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC0803 datasheet File size : 1158 kB |
| Request For quote: | Find where to buy ADC0803
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Datasheet text preview:
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters
November 1999
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters
General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and ADC0805 are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric ladder -- similar to the 256R products. These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATE output latches directly driving the data bus. These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfacing logic is needed. Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. n Differential analog voltage inputs n Logic inputs and outputs meet both MOS and TTL voltage level specifications n Works with 2.5V (LM336) voltage reference n On-chip clock generator n 0V to 5V analog input voltage range with single 5V supply n No zero adjust required n 0.3" standard width 20-pin DIP package n 20-pin molded chip carrier or small outline package n Operates ratiometrically or with 5 VDC, 2.5 VDC, or analog span adjusted voltage reference
Key Specifications
n Resolution n Total error n Conversion time 8 bits
Features
n Compatible with 8080 µP derivatives -- no interfacing logic needed - access time - 135 ns n Easy interface to all microprocessors, or operates "stand alone"
± 1/4 LSB, ± 1/2 LSB and ± 1 LSB
100 µs
Connection Diagram
ADC080X Dual-In-Line and Small Outline (SO) Packages
DS005671-30
See Ordering Information
Ordering Information
TEMP RANGE ERROR 0°C TO 70°C ADC0802LCWM ADC0804LCWM M20B -- Small Outline ADC0804LCN 0°C TO 70°C -40°C TO +85°C ADC0801LCN ADC0802LCN ADC0803LCN ADC0805LCN/ADC0804LCJ N20A -- Molded DIP
± 1/4 Bit Adjusted ± 1/2 Bit Unadjusted ± 1/2 Bit Adjusted ± 1Bit Unadjusted
PACKAGE OUTLINE
Z-80 ® is a registered trademark of Zilog Corp.
© 2001 National Semiconductor Corporation
DS005671
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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
Typical Applications
DS005671-1
8080 Interface
DS005671-31
Error Specification (Includes Full-Scale, Zero Error, and Non-Linearity) Part Number ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 FullScale Adjusted VREF/2 = 2.500 VDC (No Adjustments) VREF/2 = No Connection (No Adjustments)
± 1/4 LSB ± 1/2 LSB ± / LSB
12
± 1 LSB ± 1 LSB
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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) (Note 3) Voltage Logic Control Inputs At Other Input and Outputs Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic) Surface Mount Package Vapor Phase (60 seconds) 6.5V -0.3V to +18V -0.3V to (VCC+0.3V) 260°C 300°C 215°C
Infrared (15 seconds) Storage Temperature Range Package Dissipation at TA = 25°C ESD Susceptibility (Note 10)
220°C -65°C to +150°C 875 mW 800V
Operating Ratings (Notes 1, 2)
Temperature Range ADC0804LCJ ADC0801/02/03/05LCN ADC0804LCN ADC0802/04LCWM Range of VCC TMINTATMAX -40°CTA+85°C -40°CTA+85°C 0°CTA+70°C 0°CTA+70°C 4.5 VDC to 6.3 VDC
Electrical Characteristics
The following specifications apply for VCC = 5 VDC, TMINTATMAX and fCLK = 640 kHz unless otherwise specified. Parameter ADC0801: Total Adjusted Error (Note 8) ADC0802: Total Unadjusted Error (Note 8) ADC0803: Total Adjusted Error (Note 8) ADC0804: Total Unadjusted Error (Note 8) ADC0805: Total Unadjusted Error (Note 8) VREF/2 Input Resistance (Pin 9) Analog Input Voltage Range DC Common-Mode Error Power Supply Sensitivity Conditions With Full-Scale Adj. (See Section 2.5.2) VREF/2 = 2.500 VDC With Full-Scale Adj. (See Section 2.5.2) VREF/2 = 2.500 VDC VREF/2-No Connection ADC0801/02/03/05 ADC0804 (Note 9) (Note 4) V(+) or V(-) Over Analog Input Voltage Range VCC = 5 VDC ± 10% Over Allowed VIN(+) and VIN(-) Voltage Range (Note 4) 2.5 0.75 Gnd 0.05 8.0 1.1 VCC+0.05 Min Typ Max Units LSB LSB LSB LSB LSB k k VDC LSB LSB
±/
14
± 1 /2 ± 1 /2 ±1 ±1
± 1/16 ± 1/16
±/
18
± 1 /8
AC Electrical Characteristics
The following specifications apply for VCC = 5 VDC and TMINTATMAX unless otherwise specified. Symbol TC TC fCLK CR tW(WR)L tACC t1H, t0H Parameter Conversion Time Conversion Time Clock Frequency Clock Duty Cycle Conversion Rate in Free-Running Mode Width of WR Input (Start Pulse Width) Access Time (Delay from Falling Edge of RD to Output Data Valid) TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) tWI, tRI CIN Delay from Falling Edge of WR or RD to Reset of INTR Input Capacitance of Logic Control Inputs
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Conditions fCLK = 640 kHz (Note 6) (Notes 5, 6) VCC = 5V, (Note 5) INTR tied to WR with CS = 0 VDC, fCLK = 640 kHz CS = 0 VDC (Note 7) CL = 100 pF CL = 10 pF, RL = 10k (See TRI-STATE Test Circuits)
Min 103 66 100 40 8770 100
Typ
Max 114 73
Units µs 1/fCLK kHz % conv/s ns
640
1460 60 9708
135 125
200 200
ns ns
300 5
450 7.5
ns pF
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
AC Electrical Characteristics
Symbol COUT Parameter TRI-STATE Output Capacitance (Data Buffers)
(Continued)
The following specifications apply for VCC = 5 VDC and TMINTATMAX unless otherwise specified. Conditions Min Typ 5 Max 7.5 Units pF
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) VIN (0) IIN (1) IIN (0) Logical "1" Input Voltage (Except Pin 4 CLK IN) Logical "0" Input Voltage (Except Pin 4 CLK IN) Logical "1" Input Current (All Inputs) Logical "0" Input Current (All Inputs) CLOCK IN AND CLOCK R VT+ VT- VH VOUT (0) VOUT (1) CLK IN (Pin 4) Positive Going Threshold Voltage CLK IN (Pin 4) Negative Going Threshold Voltage CLK IN (Pin 4) Hysteresis (VT+)-(VT-) Logical "0" CLK R Output Voltage Logical "1" CLK R Output Voltage DATA OUTPUTS AND INTR VOUT (0) Logical "0" Output Voltage Data Outputs INTR Output VOUT (1) VOUT (1) IOUT ISOURCE ISINK POWER SUPPLY ICC Supply Current (Includes Ladder Current) ADC0801/02/03/04LCJ/05 ADC0804LCN/LCWM fCLK = 640 kHz, VREF/2 = NC, TA = 25°C and CS = 5V 1.1 1.9 1.8 2.5 mA mA Logical "1" Output Voltage Logical "1" Output Voltage TRI-STATE Disabled Output Leakage (All Data Buffers) IOUT = 1.6 mA, VCC = 4.75 VDC IOUT = 1.0 mA, VCC = 4.75 VDC IO = -360 µA, VCC = 4.75 VDC IO = -10 µA, VCC = 4.75 VDC VOUT = 0 VDC VOUT = 5 VDC VOUT Short to Gnd, TA = 25°C VOUT Short to VCC, TA = 25°C 4.5 9.0 6 16 2.4 4.5 -3 3 0.4 0.4 VDC VDC VDC VDC µADC µADC mADC mADC IO = 360 µA VCC = 4.75 VDC IO = -360 µA VCC = 4.75 VDC 2.4 VDC 0.4 VDC 0.6 1.3 2.0 VDC 1.5 1.8 2.1 VDC 2.7 3.1 3.5 VDC VIN = 0 VDC -1 -0.005 µADC VIN = 5 VDC 0.005 1 µADC VCC = 4.75 VDC 0.8 VDC VCC = 5.25 VDC 2.0 15 VDC
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd. Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC. Note 4: For VIN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 4 and section 2.0.
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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
AC Electrical Characteristics
(Continued)
Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7. Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 k. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 k. Note 10: Human body model, 100 pF discharged through a 1.5 k resistor.
Typical Performance Characteristics
Logic Input Threshold Voltage vs. Supply Voltage Delay From Falling Edge of RD to Output Data Valid vs. Load Capacitance CLK IN Schmitt Trip Levels vs. Supply Voltage
DS005671-38 DS005671-39
DS005671-40
fCLK vs. Clock Capacitor
Full-Scale Error vs Conversion Time
Effect of Unadjusted Offset Error vs. VREF/2 Voltage
DS005671-41 DS005671-42 DS005671-43
Output Current vs Temperature
Power Supply Current vs Temperature (Note 9)
Linearity Error at Low VREF/2 Voltages
DS005671-44 DS005671-45
DS005671-46
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