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Details, datasheet, quote on part number:ADC0819
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| Part: | ADC0819 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => <10 bit |
| Description: | 8-bit Serial I/o A/D Converter With 19-channel Multiplexer (discontinued) |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC0819 datasheet File size : 286 kB |
| Request For quote: | Find where to buy ADC0819
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Datasheet text preview:
ADC0819 8-Bit Serial I O A D Converter with 19-Channel Multiplexer
December 1994
ADC0819 8-Bit Serial I O A D Converter with 19-Channel Multiplexer
General Description
The ADC0819 is an 8-Bit successive approximation A D converter with simultaneous serial I O The serial input controls an analog multiplexer which selects from 19 input A channels or an internal half scale test voltage n input sample-and-hold is implemented by a capacitive reference ladder and sampled data comparator This allows S the input signal to vary during the conversion cycle eparate serial I O and conversion clock inputs are providF ed to facilitate the interface to various microprocessors Y Y Y Y Y Ratiometric or absolute voltage referencing No zero or full-scale adjust required Internally addressable test voltage 0V to 5V input range with single 5V power supply TTL MOS input output compatible 28-pin molded chip carrier or 28-pin molded DIP
Key Specifications
Y Y Y Y Y
eatures
Separate asynchronous converter clock and serial data Y I O clock Y 19-Channel multiplexer with 5-Bit serial address logic Built-in sample and hold function
Y
Resolution Total unadjusted error Single supply Low Power Conversion Time
g
8-Bits LSB and g 1LSB 5VDC 15 mW 16 ms
Y
Connection Diagrams
Molded Chip Carrier (PCC) Package
Functional Diagram
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Top View Order Number ADC0819BCV CCV See NS Package Number V28A Dual-In-Line Package
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Top View Order Number ADC0819BCN CIN See NS Package Number N28B
C1995 National Semiconductor Corporation
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RRD-B30M115 Printed in U S A
Absolute Maximum Ratings (Notes 1
2) Lead Temperature (Soldering 10 sec ) Dual-In-Line Package (Plastic) Surface Mount Package Vapor Phase (60 sec ) Infrared (15 sec ) ESD Susceptibility (Note 11) 260 C 215 C 220 C 2000V 2) 4 5 VDC to 6 0 VDC TMIN s TA s TMAX C s TA s a 85 C 0 C s TA s a 70 C
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage (VCC) Voltage Inputs and Outputs Input Current Per Pin (Note 3) Total Package Input Current (Note 3) Storage Temperature Package Dissipation at TA e 25 C
b 65
6 5V
b 0 3V to VCC a 0 3V
g 5mA g 20mA
Operating Ratings (Notes 1
Supply Voltage (VCC) Temperature Range ADC0819BCV ADC0819CCV ADC0819BCN ADC0819CIN
C to a 150 C
875 mW
b 40
b 40
C s TA s a 85 C
Electrical Characteristics
The following specifications apply for VCC e 5V VREF e 5V w2 CLK e 2 097 MHz unless otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C T Parameter Conditions ypical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS Maximum Total Unadjusted Error ADC0819BCV BCN ADC0819CCV CIN Minimum Reference Input Resistance Maximum Reference Input Resistance Maximum Analog Input Range Minimum Analog Input Range On Channel Leakage Current (Note 9) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V (Note 9) Off Channel Leakage Current (Note 9) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V (Note 9) Minimum VTEST Internal Test Voltage Maximum VTEST Internal Test Voltage DIGITAL AND DC CHARACTERISTICS VIN(1) Logical ``1'' Input Voltage (Min) VIN(0) Logical ``0'' Input Voltage (Max) IIN(1) Logical ``1'' Input Current (Max) IIN(0) Logical ``0'' Input Current (Max) VCC e 5 25V VCC e 4 75V VIN e 5 0V VIN e 0V 0 005
b 0 005
VREF e 5 00 VDC (Note 4)
g g1
g
g1
LSB LSB kX kX V V nA nA
8 8 (Note 5) 11 VCC a 0 05 GNDb0 05 400
b 400
5 11 VCC a 0 05 GNDb0 05 1000
b 1000
b 400
b 1000
nA nA
400
1000
VREF e VCC CH 19 Selected VREF e VCC CH 19 Selected
125 130
125 130
(Note 10) Counts (Note 10) Counts
20 08 25
b2 5
20 08 25
b2 5
V V mA mA
2
Electrical Characteristics (Continued) The following specifications apply for VCC e 5V VREF e 5V w2 CLK e 2 097 MHz unless otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C T
Parameter Conditions ypical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units
DIGITAL AND DC CHARACTERISTICS (Continued) VOUT(1) Logical ``1'' Output Voltage (Min) VOUT(0) Logical ``0'' Output Voltage (Max) IOUT TRI-STATE Output Current (Max) ISOURCE Output Source Current (Min) ISINK Output Sink Current (Min) ICC Supply Current (Max) IREF (Max) AC CHARACTERISTICS Parameter w CLK w Clock Frequency SCLK Serial Data Clock Frequency TC Conversion Process Time MIN MAX MIN MAX Not Including MUX Addressing and MAX Analog Input Sampling Times MIN MAX MIN Conditions Tested Typical Limit (Note 6) (Note 7) Design Limit (Note 8) 10 21 50 525 26 32 1 3 4 w2CLK a 0 MIN MAX tHDI Minimum DI Hold Time from SCLK Rising Edge tHDO Minimum DO Hold Time from SCLK Falling Edge tSDI Minimum DI Set up Time to SCLK Rising Edge tDDO Maximum Delay From SCLK Falling Edge to DO Data Valid tTRI Maximum DO Hold Time CS Rising edge to DO TRI STATE RL e CL e k pF RL e CL e k pF tset-up a 8 SCLK t CS(min) a 26 w2CLK 0 10 400 250 150 1 2 SCLK sec ns sec sec ns ns ns ns ns w cycles w cycles KHz Units VCC e 4 75V IOUT e b360 mA IOUT e b10 mA VCC e 5 25V IOUT e 1 6 mA VOUT e 0V VOUT e 5V VOUT e 0V VOUT e VCC CS e 1 VREF Open VREF e 5V
b 0 01
24 45 04
b3
24 45 04
b3
V V V mA mA mA mA mA mA
0 01
b 14
3
b6 5
3
b6 5
16 1 07
80 25 1
80 25 1
MHz
tACC Access Time Delay From CS Falling Edge to DO Data Valid tSET UP Minimum Set up Time of CS Falling Edge to SCLK Rising Edge tHCS CS Hold Time After the Falling Edge of SCLK t CS Total CS Low Time
RL e k CL e pF
3
Electrical Characteristics The following specifications apply for VCC e 5V tr e tf e 20 ns VREF e 5V unless otherwise specified Boldface limits apply from TMIN to TMAX all other limTs TA e TJ e 25 C it
Parameter AC CHARACTERISTICS (Continued) tCA Analog Sampling Time tRDO Maximum DO Rise Time tFDO Maximum DO Fall Time CIN Maximum Input Capacitance After Address Is Latched CS e Low RL e 30 kX CL e 100 pf RL e 30 kX CL e 100 pf All Others ``TRI-STATE'' to ``HIGH'' State ``LOW'' to ``HIGH'' State ``TRI-STATE'' to ``LOW'' State ``HIGH'' to ``LOW'' State 75 150 75 150 11 5 150 300 150 300 3 SCLK a 1 ms 150 300 150 300 55 15 pF ns sec ns Conditions ypical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units
Analog Inputs ANOAN10 and VREF
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating N the device beyond its specified operating conditions Note 2 All voltages are measured with respect to ground ote 3 Under over voltage conditions (VIN k 0V and VIN l VCC) the maximum input current at any one pin is g 5 mA If the voltage at more than one pin exceeds VCC a 3V the total package current must be limited to 20 mA For example the maximum number of pins that can be over driven at the maximum current level of g N 5 mA is four Note 4 Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors ote 5 Two on-chip diodes are tied to each analog input which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to 5 VDC input voltage range will N erefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading th Note 6 Typicals are at 25 C and represent most likely parametric norm Note 7 Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level) Note 8 Design Limits are guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels Note 9 Channel leakage current is measured after the channel selection ote 10 1 count e VREF 256 T te 11 Human body model 100 pF discharged through a 1 5 kX resistor No
est Circuits
Leakage Current D0 Except ``TRI-STATE''
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tTRI ``TRI-STATE''
Timing Diagrams
D0 ``TRI-STATE'' Rise Fall Times
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4
Timing Diagrams (Continued)
D0 Low to High State D0 High to Low State
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Data Input and Output Timing
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Timing with a continuous SCLK
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Strobing CS High and Low will abort the present conversion and initiate a new serial I O exchange T
iming with a gated SCLK and CS Continuously Low
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Using CS To TRI-STATE D0
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Note Strobing CS Low during this time interval will abort the conversion in process 5
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