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Details, datasheet, quote on part number:ADC0820C
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| Part: | ADC0820C |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | ADC0820 - 8-Bit High Speed µP Compatible A/D Converter With Track/hold Function, Package: Soic Wide, Pin Nb=20 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC0820C datasheet File size : 480 kB |
| Request For quote: | Find where to buy ADC0820C
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Datasheet text preview:
ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function
June 1999
ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function
General Description
By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 µs conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. The input to the ADC0820 is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/µs. For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic.
Features
n n n n n n n n n 8 Bits 2.5 µs Max (RD Mode) n n n n n n Built-in track-and-hold function No missing codes No external clocking Single supply -- 5 VDC Easy interface to all microprocessors, or operates stand-alone Latched STRI-STATE output Logic inputs and outputs meet both MOS and T2L voltage level specifications Operates ratiometrically or with any reference value equal to or less than VCC 0V to 5V analog input voltage range with single 5V supply No zero or full-scale adjust required Overflow output available for cascading 0.3" standard width 20-pin DIP 20-pin molded chip carrier package 20-pin small outline package 20-pin shrink small outline package (SSOP)
Key Specifications
j Resolution j Conversion Time j Low Power j Total Unadjusted
1.5 µs Max (WR-RD Mode) 75 mW Max
Error
± 1/2 LSB and ± 1 LSB
Connection and Functional Diagrams
Dual-In-Line, Small Outline and SSOP Packages Molded Chip Carrier Package
DS005501-1
DS005501-33
Top View
© 2001 National Semiconductor Corporation
DS005501
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ADC0820
Connection and Functional Diagrams
(Continued)
DS005501-2
FIGURE 1.
Ordering Information
Part Number ADC0820BCV ADC0820BCWM ADC0820BCN ADC0820CCJ ADC0820CCWM ADC0820CIWM ADC0820CCN Total Unadjusted Error V20A -- Molded Chip Carrier Package Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C M20B -- Wide Body Small Outline N20A -- Molded DIP J20A -- Cerdip M20B -- Wide Body Small Outline M20B -- Wide Body Small Outline N20A -- Molded DIP
± 1/2 LSB
± 1 LSB
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ADC0820
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Logic Control Inputs Voltage at Other Inputs and Output Storage Temperature Range Package Dissipation at TA = 25°C Input Current at Any Pin (Note 5) Package Input Current (Note 5) ESD Susceptability (Note 9) Lead Temp. (Soldering, 10 sec.) Dual-In-Line Package (plastic) 10V -0.2V to VCC +0.2V -0.2V to VCC +0.2V -65°C to +150°C 875 mW 1 mA 4 mA 1200V 260°C
Dual-In-Line Package (ceramic) Surface Mount Package Vapor Phase (60 sec.) Infrared (15 sec.)
300°C 215°C 220°C
Operating Ratings
(Notes 1, 2) TMINTATMAX -40°CTA+85°C -40°CTA+85°C 0°CTA70°C 0°CTA70°C 0°CTA70°C 4.5V to 8V
Temperature Range ADC0820CCJ ADC0820CIWM ADC0820BCN, ADC0820CCN ADC0820BCV ADC0820BCWM, ADC0820CCWM VCC Range
Converter Characteristics
The following specifications apply for RD mode (pin 7 = 0), VCC = 5V, VREF(+) = 5V,and VREF(-) = GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25°C.
Parameter Conditions ADC0820CCJ Typ (Note 6) Resolution Total Unadjusted Error (Note 3) Minimum Reference Resistance Maximum Reference Resistance Maximum VREF(+) Input Voltage Minimum VREF(-) Input Voltage Minimum VREF(+) Input Voltage Maximum VREF(-) Input Voltage Maximum VIN Input Voltage Minimum VIN Input Voltage Maximum Analog Input Leakage Current Power Supply Sensitivity CS = VCC VIN = VCC VIN = GND VCC = 5V ± 5% 3 -3 0.3 -0.3 3 -3 µA µA LSB GND-0.1 GND-0.1 GND-0.1 V VCC+0.1 VCC+0.1 VCC+0.1 V VREF(+) VREF(+) VREF(+) V VREF(-) VREF(-) VREF(-) V GND GND GND V VCC VCC VCC V 2.3 6 2.3 5.3 6 k ADC0820BCN, BCWM ADC0820CCJ ADC0820CCN, CCWM, CIWM, ADC0820CCMSA 2.3 1.00 2.3 Tested Limit (Note 7) 8 Design Limit (Note 8) ADC0820BCN, ADC0820CCN ADC0820BCV, ADC0820BCWM ADC0820CCWM, ADC0820CIWM Typ (Note 6) Tested Limit (Note 7) 8 Design Limit (Note 8) 8 Bits LSB LSB LSB LSB k Limit Units
± 1 /2 ±1 ±1 ±1
1.2
± 1 /2 ±1 ±1
± 1/16
± 1/4
± 1/16
± 1 /4
± 1 /4
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ADC0820
DC Electrical Characteristics
The following specifications apply for VCC = 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25°C.
Parameter Conditions ADC0820CCJ Typ (Note 6) VIN(1), Logical "1" Input Voltage VIN(0), Logical "0" Input Voltage IIN(1), Logical "1" Input Current IIN(0), Logical "0" Input Current VOUT(1), Logical "1" Output Voltage VIN(1) = 5V; WR VIN(1) = 5V; Mode VIN(0) = 0V; CS , RD , WR , Mode VCC = 4.75V, IOUT = -360 µA; DB0 DB7, OFL , INT VCC = 4.75V, IOUT = -10 µA; DB0 DB7, OFL , INT VOUT(0), Logical "0" Output Voltage IOUT, TRI-STATE Output Current ISOURCE, Output Source Current ISINK, Output Sink Current ICC, Supply Current VCC = 4.75V, IOUT = 1.6 mA; DB0 DB7, OFL , INT , RDY VOUT = 5V; DB0 DB7, RDY VOUT = 0V; DB0 DB7, RDY VOUT = 0V; DB0 DB7, OFL INT VOUT = 5V; DB0 DB7, OFL , INT , RDY CS = WR = RD = 0 7.5 15 7.5 13 15 mA 0.1 -0.1 -12 -9 14 3 -3 -6 -4.0 7 0.1 -0.1 -12 -9 14 0.3 -0.3 -7.2 -5.3 8.4 3 -3 -6 -4.0 7 µA µA mA mA mA 0.4 0.34 0.4 V 4.5 4.6 4.5 V 2.4 2.8 2.4 V VCC = 4.75V VCC = 5.25V CS , WR , RD Mode CS , WR , RD Mode VIN(1) = 5V; CS , RD 0.005 0.1 50 -0.005 Tested Limit (Note 7) 2.0 3.5 0.8 1.5 1 3 200 -1 0.005 0.1 50 -0.005 0.3 170 Design Limit (Note 8) ADC0820BCN, ADC0820CCN ADC0820BCV, ADC0820BCWM ADC0820CCWM, ADC0820CIWM Typ (Note 6) Tested Limit (Note 7) 2.0 3.5 0.8 1.5 Design Limit (Note 8) 2.0 3.5 0.8 1.5 1 3 200 -1 V V V V µA µA µA µA Limit Units
AC Electrical Characteristics
The following specifications apply for VCC = 5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(-) = 0V and TA = 25°C unless otherwise specified. Typ Parameter tCRD, Conversion Time for RD Mode tACC0, Access Time (Delay from Falling Edge of RD to Output Valid) tCWR-RD, Conversion Time for WR-RD Mode tWR, Write Time tRD, Read Time Min Max Min Pin 7 = VCC; tWR = 600 ns, tRD = 600 ns; Figures 3, 4 Pin 7 = VCC; Figures 3, 4 (Note 4) See Graph Pin 7 = VCC; Figures 3, 4 (Note 4) See Graph tACC1, Access Time (Delay from Falling Edge of RD to Output Valid) Pin 7 = VCC, tRD < tI; Figure 3 CL = 15 pF CL = 100 pF 190 210 280 320 ns ns 50 600 600 ns µs ns 1.52 µs Conditions Pin 7 = 0, Figure 2 Pin 7 = 0, Figure 2 (Note 6) 1.6 tCRD+20 Tested Limit (Note 7) Design Limit (Note 8) 2.5 tCRD+50 µs ns Units
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ADC0820
AC Electrical Characteristics
(Continued)
The following specifications apply for VCC = 5V, tr = tf = 20 ns, VREF(+) = 5V, VREF(-) = 0V and TA = 25°C unless otherwise specified. Typ Parameter tACC2, Access Time (Delay from Falling Edge of RD to Output Valid) tACC3, Access Time (Delay from Rising Edge of RDY to Output Valid) tI, Internal Comparison Time t1H, t0H, TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) tINTL, Delay from Rising Edge of WR to Falling Edge of INT tINTH, Delay from Rising Edge of RD to Rising Edge of INT tINTHWR, Delay from Rising Edge of WR to Rising Edge of INT tRDY, Delay from CS to RDY tID, Delay from INT to Output Valid tRI, Delay from RD to INT tP, Delay from End of Conversion to Next Conversion Slew Rate, Tracking CVIN, Analog Input Capacitance COUT, Logic Output Capacitance CIN, Logic Input Capacitance Pin 7 = VCC, CL = 50 pF tRD > tI; Figure 4 tRD tI; Figure 4 CL = 15 pF CL = 100 pF RPULLUP = 1k and CL = 15 pF 70 90 30 120 150 ns ns ns (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units
Pin 7 = VCC; Figures 4, 5 CL = 50 pF RL = 1k, CL = 10 pF
800 100
1300 200
ns ns
Figures 2, 3, 4
CL = 50 pFc
Figure 5, CL = 50 pF Figure 2, CL = 50 pF, Pin 7 = 0 Figure 5
Pin 7 = VCC, tRD < tI
Figure 3 Figures 2, 3, 4, 5
(Note 4) See Graph
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified. Note 3: Total unadjusted error includes offset, full-scale, and linearity errors. Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs tWR and Accuracy vs tRD graphs. Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN V+) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four. Note 6: Typicals are at 25°C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 9: Human body model, 100 pF discharaged through a 1.5 k resistor.
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