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Details, datasheet, quote on part number:ADC0852CCN
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| Part: | ADC0852CCN |
| Category: | Analog & Mixed-Signal Processing => Comparators |
| Description: | Multiplexed Comparator With 8-bit Reference Divider |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC0852CCN datasheet File size : 335 kB |
| Request For quote: | Find where to buy ADC0852CCN
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Datasheet text preview:
ADC0852 ADC0854 Multiplexed Comparator with 8-Bit Reference Divider
April 1995
ADC0852 ADC0854 Multiplexed Comparator with 8-Bit Reference Divider
General Description
The ADC0852 and ADC0854 are CMOS devices that combine a versatile analog input multiplexer voltage comparator and an 8-bit DAC which provides the comparator's threshold voltage (VTH) The comparator provides a ``1-bit'' output as a result of a comparison between the analog input and the DAC's output This allows for easy implementation of set-point on-off or ``bang-bang'' control systems with T several advantages over previous devices he ADC0854 has a 4 input multiplexer that can be software configured for single ended pseudo-differential and full-differential modes of operation In addition the DAC's referT ence input is brought out to allow for reduction of the span he ADC0852 has a two input multiplexer that can be configured as 2 single-ended or 1 differential input pair The D T AC reference input is internally tied to VCC he multiplexer and 8-bit DAC are programmed via a serial data input word Once programmed the output is updated once each clock cycle up to a maximum clock rate of F 0 kHz 40
eatures
Y Y Y Y Y Y
2 or 4 channel multiplexer Differential or Single-ended input software controlled Serial digital data interface 256 programmable reference voltage levels Continuous comparison after programming Fixed ratiometric or reduced span reference capability (ADC 0854)
Key Specifications
Y Y Y
Accuracy g LSB or g 1 LSB of Reference (0 2%) Single 5V power supply Low Power 15 mW
TL H 5521 1
FIC URE 1 ADC0854 Simplified Block Diagram (ADC0852 has 2 input channels G OM tied to GND VREF tied to VCC V a omitted and one GND connection) 2 Channel and 4 Channel Pin Out ADC0852 2-CHANNEL MUX Dual-In-Line Package ADC0854 4-CHANNEL MUX Dual-In-Line Package
TL H 5521 10
Top View
AGND and COM internally connected to GND VREF internally connected to VCC
TL H 5521 11
Order Number ADC0852 See NS Package Number N08E
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL H 5521
Top View Order Number ADC0854 See NS Package Number N14A
RRD-B30M75 Printed in U S A
Absolute Maximum Ratings (Notes 1 and 2)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales C Office Distributors for availability and specifications urrent into V a (Note 3) Supply Voltage VCC (Note 3) Voltage Logic and Analog Inputs Input Current per Pin Input Current per Package Storage Temperature Package Dissipation at TA e 25 C (Board Mount) 15 mA 6 5V
b 0 3V to VCC a 0 3V
g 5 mA g 20 mA
Lead Temp (Soldering 10 seconds) Dual-In-Line Package (plastic) ESD Susceptibility (Note 14)
260 C 2000V
Operating Conditions
Supply Voltage VCC Temperature Range ADC0854CCN ADC0852CCN 4 5VDC to 6 3VDC TMIN s TA s TMAX 0 C s TA s 70 C
b 65
C to a 150 C
0 8W
V lectrical Characteristics The following specifications apply for VCC e V a e 5V (no V a on ADC0852) E REF s VCC a 0 1V fCLK e 250 kHz unless otherwise specified Boldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C A DC0852CCN ADC0854CCN Parameter Conditions Typ (Note 4) Tested Limit (Note 5) Design Limit (Note 6) Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error (Note 7) ADC0852 4 CCN Comparator Offset ADC0852 4 CCN Minimum Total Ladder Resistance Maximum Total Ladder Resistance Minimum Common-Mode Input (Note 8) Maximum Common-Mode Input (Note 8) DC Common-Mode Error Power Supply Sensitivity VZ Internal diode breakdown at V a (Note 3) MIN MAX On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V VCC e 5V g 5% 15 mA into V a 63 85 b1
b 200
VREF Forced to 5 000 VDC
g1 g1
LSB mV kX kX V V LSB LSB V V mA nA mA nA
25 ADC0854 (Note 15) ADC0854 (Note 15) All MUX Inputs and COM Input All MUX Inputs and COM Input
g g
20 13 54 GND 0 05 VCC a 0 05 g g 13 59 GND 0 05 VCC a 0 05 g g
35 35
IOFF Off Channel Leakage Current (Note 9)
a1
a 200
2
Electrical Characteristics (Continued) T Bhe following specifications apply for VCC e V a e 5V (no V a on ADC0852) fCLK e 250 kHz unless otherwise specified oldface limits apply from TMIN to TMAX all other limits TA e TJ e 25 C A
DC0852CCN ADC0854CCN Parameter Conditions Typ (Note 4) Tested Limit (Note 5) Design Limit (Note 6) Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) ION On Channel Leakage Current (Note 9) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V DIGITAL AND DC CHARACTERISTICS VIN(1) Logical ``1'' Input Voltage VIN(0) Logical ``0'' Input Voltage IIN(1) Logical ``1'' Input Current IIN(0) Logical ``0'' Input Current VOUT(1) Logical ``1'' Output Voltage VOUT(0) Logical ``0'' Output oltage IOUT TRI-STATE Output Current (DO) ISOURCE ISINK ICC Supply Current ADC0852 ICC Supply Current ADC0854 (Note 3) VCC e 5 25V VCC e 4 75V VIN e VCC VIN e 0V VCC e 4 75V IOUT e b360 mA IOUT e b10 mA IOUT e 1 6 mA VCC e 4 75V CS e Logical ``1'' VOUT e 0 4V VOUT e 5V VOUT Short to GND VOUT Short to VCC Includes DAC Ladder Current Does not Include DAC Ladder Current
b0 1
a1
a 200
mA nA mA nA
b1
b 200
20 08 0 005
b 0 005
20 08 1
b1
V V mA mA
1
b1
24 45 04
b3
24 45 04
b3
V V V mA mA mA mA mA mA
01
b 14
3
b7 5
3
b6 5
16 27 09
90 65 25
80 65 25
3
AC Characteristics tr e tf e 20 ns
Symbol fCLK tD1 tr Parameter Clock Frequency (Note 12) Rising Edge of Clock to ``DO'' Enabled Comparator Response Time (Note 13) Clock Duty Cycle (Note 10) tSET-UP CS Falling Edge or Data Input Valid to CLK Rising Edge Data Input Valid after CLK Rising Edge CLK Falling Edge to Output Data Valid (Note 11) Rising Edge of CS to Data Output Hi-Z Capacitance of Logic Input Capacitance of Logic Outputs MIN MAX MAX MIN MAX
TA e 25 C Conditions Typ (Note 4) Tested Limit (Note 5) 10 400 Design Limit (Note 6) Units kHz kHz ns 1 fCLK % % 250 ns
CL e 100 pF Not Including Addressing Time
650
1000 2 a 1 ms 40 60
tHOLD tpd1 tpd0
MIN MAX CL e 100 pF 650
90 1000
ns ns
t1H t0H
MAX
CL e 10 pF RL e 10k CL e 100 pF RL e 2k (see TRI-STATE Test Circuits)
125 500 5 5
250 500
ns ns pF pF
CIN COUT
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when N operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to ground ote 3 Internal zener diodes (approx 7V) are connected from V a to GND and VCC to GND The zener at V a can operate as a shunt regulator and is connected to VCC via a conventional diode Since the zener voltage equals the A D's breakdown voltage the diode ensures that VCC will be below breakdown when the device is powered from V a Functionality is therefore guaranteed for V a operation even though the resultant voltage at VCC may exceed the specified Absolute N ax of 6 5V It is recommended that a resistor be used to limit the max current into V a M Note 4 Typicals are at 25 C and represent most likely parametric norm Note 5 Tested and guaranteed to National AOQL (Average Outgoing Quality Level) Note 6 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels Note 7 Total unadjusted error includes comparator offset DAC linearity and multiplexer error It is expressed in LSBs of the threshold DAC's input code ote 8 For VIN( b ) t VIN( a ) the output will be 0 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance N and loading Note 9 Leakage current is measured with the clock not switching ote 10 A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of th N ese limits then 1 6 mS s CLK Low s 60 mS and 1 6 mS s CLK HIGH s % ote 11 With CS low and programming complete D0 is updated on each falling CLK edge However each new output is based on the comparison completed 0 5 N clock cycles prior (see Figure 5 ) Note 12 Error specs are not guaranteed at 400 kHz (see graph Comparator Error vs fCLK) ote 13 See text section 1 2 Note 14 Human body model 100 pF discharged through a 1 5 kX resistor ote 15 Because the reference ladder of the ADC0852 is internally connected to VCC ladder resistance cannot be directly tested for the ADC0852 Ladder current is included in the ADC0852's supply current specification 4
Typical Performance Characteristics
Internal DAC Linearity Error vs VREF Voltage Internal DAC Linearity Error vs Temperature
Comparator Error vs fCLK
Output Current vs Temperature
Comparator Offset vs Temperature
IREF Reference Current vs Temp ADC0854
ICC Power Supply Current vs Temperature ADC0854
CC Power Supply Current vs fCLK ADC0854 I
TL H 5521 2
For ADC0852 add IREF
5
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