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Details, datasheet, quote on part number:ADC08832IMMX
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| Part: | ADC08832IMMX |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | ADC08832 - 8-Bit Serial I/o CMOS A/D Converters With Multiplexer And Sample/hold Function, Package: Mini Soic, Pin Nb=8 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC08832IMMX datasheet File size : 499 kB |
| Request For quote: | Find where to buy ADC08832IMMX
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Datasheet text preview:
ADC08831/ADC08832 8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold Function
September 1999
ADC08831/ADC08832 8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold Function
General Description
The ADC08831/ADC08832 are 8-bit successive approximation Analog to Digital converters with 3-wire serial interfaces and a configurable input multiplexer for 2 channels. The serial I/O will interface to COPSTMfamily of micro-controllers, PLD's, microprocessors, DSP's, or shift registers. The serial I/O is configured to comply with the NSC MICROWIRETM serial data exchange standard. To minimize total power consumption, the ADC08831/ADC08832 automatically go into low power mode whenever they are not performing conversions. A track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion. The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. The voltage reference input can be adjusted to allow encoding of small analog voltage spans to the full 8-bits of resolution. n Remote sensing in noisy environments n Instrumentation n Embedded Systems
Features
n n n n n n n 3-wire serial digital data link requires few I/O pins Analog input track/hold function 2-channel input multiplexer option with address logic Analog input voltage range from GND to VCC No zero or full scale adjustment required TTL/CMOS input/output compatible Superior pin compatible replacement for ADC0831/2
Key Specifications
n n n n n n n Resolution: 8 bits Conversion time (fC = 2 MHz): 4µs (max) Power dissipation: 8.5mW (typ) Low power mode: 3.0mW (typ) Single supply: 5VDC Total unadjusted error: ± 1LSB No missing codes over temperature
Applications
n Digitizing sensors and waveforms n Process control monitoring
Typical Application
DS100108-44
DS100108-43
COPSTM is a trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. TRI-STATETM
© 1999 National Semiconductor Corporation
DS100108
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Connection Diagrams
ADC08831 Wide Body SO Packages ADC08832 Wide Body SO Packages
DS100108-4
DS100108-3
ADC08831 N,M,MM Packages
ADC08832 N,M,MM Packages
DS100108-2
DS100108-1
Ordering Information
Temperature Range Industrial (-40°C TJ +85°C) ADC08831IN ADC08832IN ADC08831IWM, ADC08832IWM, ADC08831IM, ADC08832IM, ADC08831IMM, ADC08832IMM, N08E M14B M08A MUA08A Package
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Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Inputs and Outputs Input Current at Any Pin (Note 4) Package Input Current (Note 4) ESD Susceptibility (Note 6) Human Body Model Machine Model Junction Temperature (Note 5) Storage Temperature Range 6.5V -0.3V to VCC + 0.3V ± 5 mA ± 20 mA 2000V 200V 150°C -65° C to 150°C
Mounting Temperature Lead Temp. (soldering, 10 sec) Infrared (10 sec)
260°C 215°C
Operating Ratings(Notes 2, 3)
Temperature Range Supply Voltage Thermal Resistance (jA) SO Package, 8-pin Surface Mount MSOP, 8-pin Surface Mount SO Package, 14-pin Surface Mount N Package, 8-pin Clock Frequency -40°C TJ +85°C 4.5 V to 6.0 V 190°C/W 235°C/W 145°C/W 122°C/W 10kHzfCLK2MHz
Electrical Characteristics
The following specifications apply for VCC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) LSB (max) LSB LSB LSB LSB 2.8 5.9 (VCC + 0.05) (GND - 0.05) k (min) k (max) V (max) V (min) LSB (max) LSB (max) LSB (max) µA (max) µA (min) µA (min) µA (max)
CONVERTER AND MULTIPLEXER CHARACTERISTICS TUE Total Unadjusted Error Offset Error DNL INL FS RREF VIN Differential NonLinearity Integral NonLinearity Full Scale Error Reference Input Resistance Analog Input Voltage DC Common-Mode Error Power Supply Sensitivity On Channel Leakage Current (Note 13) VCC = 5V ± 10%, VCC = 5V ± 5% On Channel = 5V, Off Channel = 0V On Channel = 0V Off Channel = 5V On Channel = 5V, Off Channel = 0V On Channel = 0V, Off Channel = 5V (Note 11) (Note 12) (Note 10)
± 0.3 ± 0.2 ± 0.2 ± 0.2 ± 0.3
3.5
±1
± 1/4 ± 1/4 ± 1/4
0.2 1 -0.2 -1 -0.2 -1 0.2 1 2.0 0.8
Off Channel Leakage Current (Note 13)
DC CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current Logical "1" Output Voltage VIN = 5.0V VIN = 0V VCC = 4.75V: IOUT = -360 µA IOUT = -10 µA VCC = 4.75V IOUT = 1.6 mA VOUT = 0V VOUT = 5V VOUT = 0V VOUT = VCC
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V (min) V (max) µA (max) µA (max) V (min) V (min) V (max) µA (max) µA (max) mA (max) mA (min)
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0.05 0.05
+1 -1 2.4 4.5 0.4 -3.0 3.0 -6.5 8.0
VOUT(0) IOUT ISOURCE ISINK
Logical "0" Output Voltage TRI-STATE Output Current Output Source Current Output Sink Current
Electrical Characteristics
Symbol Parameter
(Continued)
The following specifications apply for VCC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. Conditions Typical (Note 8) 0.6 1.7 1.3 2.4 Limits (Note 9) 1.0 2.4 1.8 3.5 Units (Limits) mA (max) mA (max) mA (max) mA (max)
DC CHARACTERISTICS ICC ICC Supply Current CLK = VCC ADC08831 CS = VCC CS = LOW CS = VCC CS = LOW
Supply Current ADC08832 CLK = VCC (Note 16)
Electrical Characteristics
The following specifications apply for VCC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. Symbol fCLK Parameter Clock Frequency Clock Duty Cycle (Note 14) TC tCA tSET-UP tHOLD tpd1, tpd0 Conversion Time (Not Including MUX Addressing Time) Acquisition Time CS Falling Edge or Data Input Valid to CLK Rising Edge Data Input Valid after CLK Rising Edge CLK Falling Edge to Output Data Valid (Note 15) TRI-STATE Delay from Rising Edge of CS to Data Output and SARS Hi-Z Capacitance of Analog Input (Note 17) Capacitance of Logic Inputs Capacitance of Logic Outputs CL = 100 pF: Data MSB First Data LSB First CL = 10 pF, RL = 10 k (see TRI-STATE Test Circuits) CL = 100 pF, RL = 2 k fCLK = 2MHz Conditions Typical (Note 8) Limits (Note 9) 2 40 60 8 4
12
Units (Limits) MHz (max) % (min) % (max) 1/fCLK (max) µs (max) 1/fCLK (max) ns (min) ns (min)
/
25 20
250 200 50 180 13 5 5
ns (max) ns (max) ns ns (max) pF pF pF
t1H, t0H
CIN CIN COUT
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Dynamic Characteristics
The following specifications apply for VCC = 5V, fCLK = 2MHz, TA = 25°C, RSOURCE = 50, fIN = 45kHz, VIN = 5VP, VREF = 5V, non-coherent 2048 samples with windowing. Symbol fS SNR THD SINAD ENOB SFDR Sampling Rate Parameter ADC08831 ADC08832 Conditions fCLK/11 fCLK/13 (Note 21) 48.5 -59.5 48.0 7.7 62.5 Typical (Note 8) Limits (Note 9) 181 153 Units (Limits) ksps ksps dB dB dB Bits dB
Signal-to -Noise Ratio (Note 19) Total Harmonic Distortion (Note 20) Signal-to -Noise and Distortion Effective Number Of Bits (Note 18) Spurious Free Dynamic Range
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: All voltages are measured with respect to GND = 0 VDC, unless otherwise specified. Note 4: When the input voltage VIN at any pin exceeds the power supplies (VIN VCC,) the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins. Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 6: Human body model, 100 pF capacitor discharged through a 1.5 k resistor. The machine mode is a 200pF capacitor discharged directly into each pin. Note 7: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or Linear Data Book section "Surface Mount" for other methods of soldering surface mount devices. Note 8: Typicals are at TJ = 25°C and represent the most likely parametric norm. Note 9: Guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: Total Unadjusted Error (TUE) includes offset, full-scale, linearity, multiplexer errors. Note 11: It is not tested for the ADC08832. Note 12: For VIN(-) VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Functional Block Diagram) which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. During testing at low VCC levels (e.g., 4.5V), high level analog inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining off channel tied low (0 VDC), total current flow through the off channel is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channel is again measured. The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured. Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or low is 60 µs. Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow for comparator response time. Note 16: For the ADC08832 Vref is internally tied to VCC, therefore, for the ADC08832 reference current is included in the supply current. Note 17: Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor. Note 18: Effective Number Of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD-1.76)/ 6.02. Note 19: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in it's calculation. Note 20: The contributions from the first 6 harmonics are used in the calculation of the THD. Note 21: The maximum sampling rate is slightly less than fCLK/11 if CS is reset in less than one clock period.
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