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Details, datasheet, quote on part number:ADC1251BI
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| Part: | ADC1251BI |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | ADC1251 - Self-calibrating 12-Bit Plus Sign A/D Converter With Sample And Hold, Package: Cerdip, Pin Nb=24 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC1251BI datasheet File size : 308 kB |
| Request For quote: | Find where to buy ADC1251BI
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Datasheet text preview:
ADC1251 Self-Calibrating 12-Bit Plus Sign A D Converter with Sample-and-Hold
December 1994
ADC1251 Self-Calibrating 12-Bit Plus Sign A D Converter with Sample-and-Hold
General Description
The ADC1251 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter On request the ADC1251 goes through a self-calibration cycle that adjusts for any zero full scale or linearity errors The ADC1251 also has the ability to go through an Auto-Zero cycle that corT rects the zero error during every conversion he analog input to the ADC1251 is tracked and held by the internal circuitry so an external sample-and-hold is not required The ADC1251 has an S H control input which directly controls the track-and-hold state of the A D A unipolar analog input voltage range (0 to a 5V) or a bipolar range (b T 5V to a 5V) can be accommodated with g 5V supplies he 13-bit data result is available on the eight outputs of the A T DC1251 in two bytes high-byte first and sign extended he digital inputs and outputs are compatible with TTL or CMOS logic levels F
Y Y Y Y
8-bit mP DSP interface Bipolar input range with a single a 5V reference No missing codes over temperature TTL MOS input output compatible
Key Specifications
Y Y Y Y Y Y Y
Resolution Conversion Time Sampling Rate Linearity Error Zero Error Full Scale Error Power Consumption
12 bits plus sign 8 ms (max) 83 kHz (max) g 0 6 LSB ( g 0 0146%) (max) g 1 LSB (max) g 1 5 LSB (max) g 5V 113 mW (max)
Applications
Y Y Y
eatures
Y Y
Digital signal processing High resolution process control Instrumentation
Self-calibration provides excellent temperature stability Internal sample-and-hold
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
TL H 11024 2
Top View
Ordering Information
Industrial (b40 C s TA s a 85 C) ADC1251BIJ ADC1251CIJ
TL H 11024 1
Package J 24A
Military Package (b55 C s TA s a 125 C) ADC1251CMJ ADC1251CMJ 883 J24A
C TRI-STATE is a registered trademark of National Semiconductor Corporation 1995 National Semiconductor Corporation TL H 11024 RRD-B30M115 Printed in U S A
Absolute Maximum Ratings (Notes 1
2)
Operating Ratings (Notes 1
Temperature Range ADC1251BIJ ADC1251CIJ ADC1251CMJ ADC1251CMJ 883 DVCC and AVCC Voltage (Notes 6 7) Negative Supply Voltage (Vb) Reference Voltage (VREF Notes 6 7)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage (VCC e DVCC e AVCC) Negative Supply Voltage (Vb) 6 5V
b 6 5V
2) TMIN s TA s TMAX b 40 C s TA s a 85 C b 55 C s TA s a 125 C b 55 C s TA s a 125 C 4 5V to 5 5V
b 4 5V to b 5 5V
b 0 3V to (VCC a 0 3V) Voltage at Logic Control Inputs Voltage at Analog Inputs (VREF VIN) (Vb b0 3V) to (VCC a 0 3V) 0 3V AVCC-DVCC (Note 7)
3 5V to AVCC a 50 mV
Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation at 25 C (Note 4) Storage Temperature Range ESD Susceptability (Note 5) Soldering Information J Package (10 sec )
g 5 mA g 20 mA
875 mW
b 65
C to a 150 C
2000V 300 C
Converter Electrical Characteristics
The following specifications apply for VCC e DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V AZ e ``1'' fCLK e 3 5 MHz and tested using WR control unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 7 and 8) Symbol Parameter Conditions Typical Limit (Note 9) (Notes 10 19) Units (Limit)
STATIC CHARACTERISTICS Positive Integral Linearity Error ADC1251BIJ ADC1251CIJ ADC1251CMJ Negative Integral Linearity Error ADC1251BIJ ADC1251CIJ ADC1251CMJ Missing Codes Zero Error (Notes 12 and 13) After Auto-Cal (Notes 11 and 12) AZ e ``0'' and fCLK e 1 75 MHz After Auto-Cal Only Positive Full-Scale Error (Note 12) AZ e ``0'' and fCLK e 1 75 MHz After Auto-Cal Only Negative Full-Scale Error (Note 12) AZ e ``0'' and fCLK e 1 75 MHz After Auto-Cal Only CREF CIN VIN VREF Input Capacitance (Note 18) Analog Input Capacitance Analog Input Voltage Power Supply Sensitivity Zero Error (Note 14) AVCC e DVCC e 5V g 5% e 4 75V V b e b 5V g 5% V Full-Scale Error REF Linearity Error g
g g
After Auto-Cal (Notes 11 12)
g0 6 g1 g1
LSB(max) LSB(max) LSB(max) LSB(max) LSB(max) LSB(max)
After Auto-Cal (Notes 11 and 12)
g0 6 g1 g1
0
g2 g2 0 g3 0 g1 5 g1 5 g2 0 g1 5 g1 5 g2 0
LSB(max) LSB(max) LSB(max) LSB(max) LSB(max) LSB(max) pF pF
80 65 Vb b 0 05 VCC a 0 05
V(min) V(max) LSB LSB LSB
2
Converter Electrical Characteristics (Continued) The following specifications apply for VCC e DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V AZ e ``1'' and fCLK e ( 3 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C Notes 6 7 and 8)
Symbol Parameter Conditions Typical (Note 9) Limit (Notes 10 19) Units (Limit)
DYNAMIC CHARACTERISTICS S (N a D) Unipolar Signal-to-Noise a Distortion Ratio (Note 17) Bipolar Signal-to-Noise a Distortion Ratio (Note 17)
b 3 dB Unipolar Full Power Bandwidth b 3 dB Bipolar Full Power Bandwidth
fIN e 1 kHz VIN e 4 85 Vp-p fIN e 20 kHz VIN e 4 85 Vp-p fIN e 1 kHz VIN e g 4 85V fIN e 20 kHz VIN e g 4 85V VIN e 4 85V (Note 17) VIN e g 4 85V (Note 17)
72 72 76 76 32 25 100 100
dB dB dB dB kHz kHz ns psrms
S (N a D)
tAp
Aperture Time Aperture Jitter
Digital and DC Electrical Characteristics
The following specifications apply for DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V and fCLK e 3 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7) Symbol VIN(1) VIN(0) IIN(1) IIN(0) VT a VTb VH V
OUT(1)
Parameter Logical ``1'' Input Voltage for All Inputs except CLK IN Logical ``0'' Input Voltage for All Inputs except CLK IN Logical ``1'' Input Current Logical ``0'' Input Current CLK IN Positive-Going Threshold Voltage CLK IN Negative-Going Threshold Voltage CLK IN Hysteresis VT a (min) b VTb(max) Logical ``1'' Output Voltage
Conditions VCC e 5 25V VCC e 4 75V VIN e 5V VIN e 0V
Typical (Note 9)
Limit (Notes 10 19) 20 08
Units (Limit) V(min) V(max) mA(max) mA(max) V(min) V(max) V(min)
0 005
b 0 005
1
b1
28 21 07 VCC e 4 75V IOUT e b360 mA IOUT e b10 mA VCC e 4 75V IOUT e 1 6 mA VOUT e 0V VOUT e 5V VOUT e 0V VOUT e 5V CS e ``1'' CS e ``1'' CS e ``1''
b 0 01
27 23 04
24 45 04
b3
V(min) V(min) V(max) mA(max) mA(max) mA(min) mA(min) mA(max) mA(max) mA(max)
VOUT(0) IOUT
Logical ``0'' Output Voltage TRI-STATE Output Leakage Current Output Source Current Output Sink Current DVCC Supply Current AVCC Supply Current Vb Supply Current
0 01
b 20
3
b6 0
ISOURCE ISINK DICC AICC Ib
20 1 4 28
80 25 10 10
3
AC Electrical Characteristics
Bhe following specifications apply for DVCC e AVCC e a 5 0V Vb e b5 0V tr e tf e 20 ns unless otherwise specified T oldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7) Symbol fCLK Parameter Clock Frequency 05 60 Clock Duty Cycle 50 40 60 tC Conversion Time Using WR to Start a Conversion 27(1 fCLK) fCLK e 3 5 MHz AZ e ``1'' fCLK e 1 75 MHz AZ e ``0'' tC Conversion Time Using S H to Start a Conversion Acquisition Time (Note 15) Internal Acquisition Time (When Using WR Control Only) Auto Zero Time a Acquisition Time fCLK e 1 75 MHz tD(EOC)L Delay from Hold Command to Falling Edge of EOC tCAL Calibration Time fCLK e 3 5 MHz tW(CAL)L Calibration Pulse Width tW(WR)L Minimum WR Pulse Width tACC Maximum Access Time (Delay from Falling Edge of RD to Output Data Valid) TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) Maximum Delay from Falling Edge of RD or WR to Reset of INT Delay between Successive RD Pulses CL e 100 pF 50 RL e 1 kX CL e 100 pF 30 70 ns(max) 95 ns(max) (Note 16) Using WR Control Using S H Control AZ e ``1'' fCLK e 3 5 MHz AZ e ``1'' RSOURCE e 50X 77 15 4 34(1 fCLK) 97 35 7(1 fCLK) 33(1 fCLK) 18 8 200 100 1399(1 fCLK) 399 60 60 27(1 fCLK) a 250 ns 7 95 15 65 34(1 fCLK) a 250 ns 9 95 35 7(1 fCLK) 33(1 fCLK) a 250 ns 19 05 350 150 1399 (1 fCLK) 400 200 200 35 Conditions Typical (Note 9) Limit (Notes 10 19) Units (Limit) MHz MHz(min) MHz(max) % %(min) %(max) (max) ms(max) ms(max) (max) ms(max) ms(min) (max) (max) ms(max) ns(max) ns(max) (max) ms(max) ns(min) ns(min)
tA tIA tZA
t0H t1H
tPD(INT) tRR
100 30
175 60
ns(max) ns(min)
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test N conditions Note 2 All voltages are measured with respect to AGND and DGND unless otherwise specified ote 3 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to 5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power N supply voltages ote 4 The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation a 1 TTL Load on each digital output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex when any inputs or outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature is PDmax e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJmax e 150 C and the typical thermal resistance (iJA) of the ADC1251 with CMJ BIJ and CIJ suffixes when board mounted is 51 C W Note 5 Human body model 100 pF discharged through a 1 5 kX resistor 4
Electrical Characteristics (Continued)
Note 6 Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than b T 50 mV This means that if AVCC and DVCC are minimum (4 75 VDC) and V is maximum ( b 4 75 VDC) the analog input full-scale voltage must be s g 4 8 VDC
L H 11024 4
Note 7 A diode exists between AVCC and DVCC as shown below
T
L H 11024 5
To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin N ote 8 Accuracy is guaranteed at fCLK e 3 5 MHz At higher or lower clock frequencies accuracy may degrade See the Typical Performance Characteristics N curves Note 9 Typicals are at TJ e 25 C and represent most likely parametric norm Note 10 Limits are guaranteed to National's AOQL (Average Outgoing Quality Level) ote 11 Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and zero For negative linearity error the straight line passes through negative full scale and zero (See Figures 1b and 1c ) N ote 12 The ADC1251's self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will re N sult in a repeatability uncertainty of g 0 20 LSB Note 13 If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started See the typical performance characteristic curves Note 14 After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes ote 15 When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the end of the interval tA therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the clock N is synchronous to the rising edge of WR then tA will end exactly 6 5 clock periods after the rising edge of WR This does not occur when S H control is used Note 16 The CAL line must be high before a conversion is started Note 17 The specifications for these parameters are valid after an Auto-Cal cycle has been completed Note 18 The ADC1251 reference ladder is composed solely of capacitors ote 19 A Military RETS Electrical Test Specification is available on request At time of printing the ADC1251CMJ 883 RETS specification complies fully with the boldface limits in this column T
FIGURE 1a Transfer Characteristic
L H 11024 6
5
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