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Details, datasheet, quote on part number:ADC12662CIV
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| Part: | ADC12662CIV |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | ADC12662 - 12-Bit, 1.5 Mhz, 200 MW A/D Converter With Input Multiplexer And Sample/Hold, Package: Plcc, Pin Nb=44 |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC12662CIV datasheet File size : 507 kB |
| Request For quote: | Find where to buy ADC12662CIV
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Datasheet text preview:
ADC12662 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold
June 2001
ADC12662 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold
General Description
Using an innovative multistep conversion technique, the 12-bit ADC12662 CMOS analog-to-digital converter digitizes signals at a 1.5 MHz sampling rate while consuming a maximum of only 200 mW on a single +5V supply. The ADC12662 performs a 12-bit conversion in three lower-resolution "flash" conversions, yielding a fast A/D without the cost and power dissipation associated with true flash approaches. The analog input voltage to the ADC12662 is tracked and held by an internal sampling circuit, allowing high frequency input signals to be accurately digitized without the need for an external sample-and-hold circuit. The ADC12662 features two sample-and-hold/flash comparator sections which allow the converter to acquire one sample while converting the previous. This pipelining technique increases conversion speed without sacrificing performance. The multiplexer output is available to the user in order to perform additional external signal processing before the signal is digitized. When the converter is not digitizing signals, it can be placed in the Standby mode; typical power consumption in this mode is 250 µW.
Features
n n n n Built-in sample-and-hold Single +5V supply Single channel or 2 channel multiplexer operation Low Power Standby mode
Key Specifications
n n n n n Sampling rate Conversion time Signal-to-Noise Ratio, fIN = 100 kHz Power consumption (fs = 1.5 MHz) No missing codes over temperature 1.5 MHz (min) 580 ns (typ) 67.5 dB (min) 200 mW (max) Guaranteed
Applications
n n n n n Digital signal processor front ends Instrumentation Disk drives Mobile telecommunications Waveform digitizers
ADC12662 Block Diagram
01187601
Ordering Information
Industrial (-40°C TA +85°) ADC12662CIV ADC12662CIVF Package V44 Plastic Leaded Chip Carrier VGZ44A Plastic Quad Flat Package
© 2001 National Semiconductor Corporation
DS011876
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ADC12662
Connection Diagrams
01187615
01187629
Top View
Top View
Pin Descriptions
AVCC These are the two positive analog supply inputs. They should always be connected to the same voltage source, but are brought out separately to allow for separate bypass capacitors. Each supply pin should be bypassed to AGND with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. This is the positive digital supply input. It should always be connected to the same voltage as the analog supply, AVCC. It should be bypassed to DGND2 with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. DGND1, DGND2 These are the power supply ground pins. There are separate analog and digital ground pins for separate bypassing of the analog and digital supplies. The ground pins should be connected to a stable, noise-free system ground. All of the ground pins should be returned to the same potential. AGND is the analog ground for the converter. DGND1 is the ground pin for the digital control lines. DGND2 is the ground return for the output databus. See Section 6.0 LAYOUT AND GROUNDING for more information. These are the TRI-STATE output pins, enabled by RD, CS, and OE. These are the analog input pins to the multiplexer. For accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mV below ground or 50 mV above VCC. This is the output of the on-board analog input multiplexer.
2
ADC IN
S0
DVCC
This is the direct input to the 12-bit sampling A/D converter. For accurate conversions, this pin should not be driven more than 50 mV below ground or 50 mV above VCC. This pin selects the analog input that will be connected to the ADC12662 during the conversion. The input is selected based on the state of S0 when EOC makes its high-to-low transition. Low selects VIN1, high selects VIN2. This pin should be tied to DGND1. This is the active low Chip Select control input. When low, this pin enables the RD, S/H, and OE inputs. This pin can be tied low. This is the active low Interrupt output. When using the Interrupt Interface Mode (Figure 1), this output goes low when a conversion has been completed and indicates that the conversion result is available in the output latches. This output is always high when RD is held low (Figure 2). This is the End-of-Conversion control output. This output is low during a conversion. This is the active low Read control input. When RD is low (and CS is low), the INT output is reset and (if OE is high) data appears on the data bus. This pin can be tied low. This is the active high Output Enable control input. This pin can be thought of as an inverted version of the RD input (see Figure 6). Data output pins DB0 DB11 are TRI-STATE when OE is low. Data appears on DB0 DB11 only when OE is high and CS and RD are both low. This pin can be tied high. This is the Sample/Hold control input. The analog input signal is held and a new conver-
MODE CS
INT
AGND,
EOC RD
DB0 DB11 VIN1, VIN2
OE
MUX OUT
S/H
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ADC12662
Pin Descriptions
PD
(Continued)
sion is initiated by the falling edge of this control input (when CS is low). This is the Power Down control input. This pin should be held high for normal operation. When this pin is pulled low, the device goes into a low power standby mode.
information. VREF+(SENSE), VREF-(SENSE) These are the positive and negative voltage reference sense pins, respectively. See Section 4, REFERENCE INPUTS, for more information. VREF/16 TEST This pin should be bypassed to AGND with a 0.1 µF ceramic capacitor. This pin should be tied to DVCC.
VREF+(FORCE), VREF-(FORCE) These are the positive and negative voltage reference force inputs, respectively. See Section 4, REFERENCE INPUTS, for more
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ADC12662
Absolute Maximum Ratings
2)
(Notes 1,
VF Package Vapor Phase (60 seconds) Infrared (15 seconds) Storage Temperature Range Maximum Junction Temperature (TJMAX) 215°C 220°C -65°C to +150°C 150°C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC = DVCC = AVCC) Voltage at Any Input or Output Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) ADC12662CIV ESD Susceptibility (Note 5) Soldering Information (Note 6) V Package, Infrared, 15 seconds 875 mW 2000V +300°C -0.3V to +6V -0.3V to VCC + 0.3V 25 mA 50 mA
Operating Ratings (Notes 1, 2)
Temperature Range ADC12662CIV, ADC12662CIVF Supply Voltage Range (DVCC = AVCC) TMIN TA TMAX -40°C TA +85°C 4.75V to 5.25V
Converter Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.5 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol Resolution Differential Linearity Error Integral Linearity Error (Note 9) Offset Error Full-Scale Error Power Supply Sensitivity (Note 15) RREF VREF(+) VREF(-) VIN Reference Resistance VREF+(SENSE) Input Voltage VREF-(SENSE) Input Voltage Input Voltage Range ADC IN Input Leakage CADC ADC IN Input Capacitance MUX On-Channel Leakage MUX Off-Channel Leakage CMUX Multiplexer Input Cap MUX Off Isolation fIN = 100 kHz AGND to AVCC - 0.3V AGND to AVCC - 0.3V To VIN1, VIN2, or ADC IN AGND to AVCC - 0.3V 0.1 25 0.1 0.1 7 92 3 3 TMIN to TMAX TMIN to TMAX TMIN to TMAX TMIN to TMAX DVCC = AVCC = 5V ± 5% 1000 Parameter Conditions Typ (Note 7) Limit (Note 8) 12 Units (Limit) Bits LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) (min) (max) V (max) V (min) V (max) V (min) µA (max) pF µA (max) µA (max) pF dB
± 0.4 ± 0.4 ± 0.3 ± 0.3
± 0.95 ± 1.5 ± 2.0 ± 1.5 ± 0.75
600 1300 AVCC AGND AVCC+0.05V AGND - 0.05V 3
Dynamic Characteristics (Note 10)
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, RS = 25, fIN = 100 kHz, 0 dB from fullscale, and fs = 1.5 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol SINAD Parameter Signal-to-Noise Plus Distortion Ratio Conditions Typ (Note 7) TMIN to TMAX 70 Limit (Note 8) 67.0 Units (Limit) dB (min)
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ADC12662
Dynamic Characteristics (Note 10)
(Continued) The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, RS = 25, fIN = 100 kHz, 0 dB from fullscale, and fs = 1.5 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Parameter Signal-to-Noise Ratio (Note 11) Total Harmonic Distortion (Note 12) Effective Number of Bits (Note 13) Intermodulation Distortion Conditions Typ (Note 7) Limit (Note 8) 67.5 -70 10.8 Units (Limit) dB (min) dBc (max) Bits (min) dBc
Symbol SNR THD ENOB IMD
TMIN to TMAX TMIN to TMAX TMIN to tMAX fIN = 88.7 kHz, 89.5 kHz
70 -80 11.3 -80
DC Electrical Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.5 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) Parameter Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current DVCC = AVCC = +4.5V, Logical "1" Output Voltage IOUT = -360 µA IOUT = -100 µA VOUT(0) IOUT COUT CIN DICC AICC ISTANDBY Logical "0" Output Voltage TRI-STATE ® Output Leakage Current TRI-STATE Output Capacitance Digital Input Capacitance DVCC Supply Current AVCC Supply Current Standby Current (DICC + AICC) PD = 0V DVCC = AVCC = +4.5V, IOUT = 1.6 mA Pins DB0 DB11 Pins DB0 DB11 0.1 5 4 2 32 50 3 37 2.4 4.25 0.4 3 V (min) V (min) V (max) µA (max) pF pF mA (max) mA (max) µA Conditions DVCC = AVCC = +5.5V DVCC = AVCC = +4.5V 0.1 0.1 Typ (Note 7) Limit (Note 8) 2.0 0.8 1.0 1.0 Units (Limit) V (min) V (max) µA (max) µA (max)
AC Electrical Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.5 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol Parameter Maximum Sampling Rate (1/tTHROUGHPUT) Conversion Time (S/H Low to EOC High) Aperture Delay (S/H Low to Input Voltage Held) S/H Pulse Width S/H Low to EOC Low 580 20 10 90 5 400 60 126 Conditions Typ (Note 7) fs tCONV tAD tS/H tEOC Limit (Note 8) 1.5 510 660 Units (Limits) MHz (min) ns (min) ns (max) ns ns (min) ns (max) ns (min) ns (max)
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