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Details, datasheet, quote on part number:ADC12762CCV
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| Part: | ADC12762CCV |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit |
| Description: | 12-bit 1.4 Mhz, 300 MW A/D Converter With Input Multiplexer And Sample/hold (obsolete) |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC12762CCV datasheet File size : 502 kB |
| Request For quote: | Find where to buy ADC12762CCV
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Datasheet text preview:
ADC12762 12-Bit, 1.4 MHz, 300 mW A/D Converter with Input Multiplexer and Sample/Hold
OBSOLETE
May 2003
ADC12762 12-Bit, 1.4 MHz, 300 mW A/D Converter with Input Multiplexer and Sample/Hold
General Description
Using an innovative multistep conversion technique, the 12bit ADC12762 CMOS analog-to-digital converter digitizes signals at a 1.4 MHz sampling rate while consuming a maximum of only 300 mW on a single +5V supply. The ADC12762 performs a 12-bit conversion in three lowerresolution "flash" conversions, yielding a fast A/D without the cost and power dissipation associated with true flash approaches. The analog input voltage to the ADC12762 is tracked and held by an internal sampling circuit, allowing high frequency input signals to be accurately digitized without the need for an external sample-and-hold circuit. The ADC12762 features two sample-and-hold/flash comparator sections which allow the converter to acquire one sample while converting the previous. This pipelining technique increases conversion speed without sacrificing performance. The multiplexer output is available to the user in order to perform additional external signal processing before the signal is digitized. When the converter is not digitizing signals, it can be placed in the Standby mode; typical power consumption in this mode is 250 µW.
Features
n Built-in sample-and-hold n Single +5V supply n Single channel or 2 channel multiplexer operation
Key Specifications
n n n n n Sampling rate Conversion time SNR, fIN = 100 kHz Power dissipation (fs = 1.4 MHz) No missing codes over temperature 1.4 MHz (min) 593 ns (typ) 67.5 dB (min) 300 mW (max) Guaranteed
Applications
n n n n n n CCD image scanners Digital signal processor front ends Instrumentation Disk drives Mobile telecommunications Waveform digitizers
ADC12762 Block Diagram
01281101
Ordering Information Commercial (0°C TA +70°C) ADC12762CCV ADC12062EVAL
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
Package V44 Plastic Leaded Chip Carrier Evaluation Board
© 2003 National Semiconductor Corporation
DS012811
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ADC12762
Absolute Maximum Ratings
2)
(Notes 1,
ADC12762CCV ESD Susceptibility (Note 5) Soldering Information (Note 6) V Package, Infrared, 15 seconds Storage Temperature Range Maximum Junction Temperature (TJMAX)
875 mW 2000V +300°C -65°C to +150°C 150°C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC = DVCC = AVCC) Voltage at Any Input or Output Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) -0.3V to +6V -0.3V to VCC + 0.3V 25 mA 50 mA
Operating Ratings (Notes 1, 2)
Temperature Range ADC12762CCV Supply Voltage Range (DVCC = AVCC) TMIN TA TMAX -0°C TA +70°C 4.75V to 5.25V
Converter Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol Resolution Differential Linearity Error Integral Linearity Error (Note 9) Offset Error Full-Scale Error Power Supply Sensitivity (Note 15) RREF VREF(+) VREF(-) VIN Reference Resistance VREF+(SENSE) Input Voltage VREF-(SENSE) Input Voltage Input Voltage Range ADC IN Input Leakage CADC ADC IN Input Capacitance MUX On-Channel Leakage MUX Off-Channel Leakage CMUX Multiplexer Input Cap MUX Off Isolation fIN = 100 kHz AGND to AVCC - 0.3V AGND to AVCC - 0.3V To VIN1, VIN2, or ADC IN AGND to AVCC - 0.3V 0.1 25 0.1 0.1 7 92 3 3 TMIN to TMAX TMIN to TMAX DVCC = AVCC = 5V ± 5% 940 TMIN to TMAX TMIN to TMAX Parameter Conditions Typ (Note 7) Limit (Note 8) 12 Units (Limit) Bits LSB (max) LSB (max) LSB (max) LSB (max) LSB (max) (min) (max) V (max) V (min) V (max) V (min) µA (max) pF µA (max) µA (max) pF dB
± 0.4 ± 0.4 ± 0.3 ± 0.3
± 0.95 ± 2.0 ± 4.0 ± 4.0 ± 0.75
500 1300 AVCC AGND AVCC+0.05V AGND - 0.05V 3
Dynamic Characteristics (Note 10)
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, RS = 25, fIN = 100 kHz, 0 dB from fullscale, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol Parameter Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio (Note 11) Total Harmonic Distortion (Note 12) Conditions Typ (Note 7) SINAD SNR THD TMIN to TMAX TMIN to TMAX TMIN to TMAX 70 70 -80 Limit (Note 8) 67.0 67.5 -70 Units (Limit) dB (min) dB (min) dBc (max)
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ADC12762
Dynamic Characteristics (Note 10)
(Continued) The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, RS = 25, fIN = 100 kHz, 0 dB from fullscale, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Parameter Effective Number of Bits (Note 13) Intermodulation Distortion Conditions Typ (Note 7) Limit (Note 8) 10.8 Units (Limit) Bits (min) dBc
Symbol
ENOB IMD
TMIN to tMAX fIN = 88.7 kHz, 89.5 kHz
11.3 -80
DC Electrical Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) Parameter Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current DVCC = AVCC = +4.5V, Logical "1" Output Voltage IOUT = -360 µA IOUT = -100 µA VOUT(0) IOUT COUT CIN DICC AICC ISTANDBY Logical "0" Output Voltage TRI-STATE ® Output Leakage Current TRI-STATE Output Capacitance Digital Input Capacitance DVCC Supply Current AVCC Supply Current Standby Current (DICC + AICC) PD = 0V DVCC = AVCC = +4.5V, IOUT = 1.6 mA Pins DB0 DB11 Pins DB0 DB11 0.1 5 4 2 32 50 10 50 2.4 4.25 0.4 3 V (min) V (min) V (max) µA (max) pF pF mA (max) mA (max) µA Conditions DVCC = AVCC = +5.5V DVCC = AVCC = +4.5V 0.1 0.1 Typ (Note 7) Limit (Note 8) 2.0 0.8 1.0 1.0 Units (Limit) V (min) V (max) µA (max) µA (max)
AC Electrical Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Symbol Parameter Maximum Sampling Rate (1/tTHROUGHPUT) Conversion Time (S/H Low to EOC High) Aperture Delay (S/H Low to Input Voltage Held) S/H Pulse Width S/H Low to EOC Low Access Time (RD Low or OE High to Data Valid) TRI-STATE Control (RD High or OE Low to Databus TRI-STATE) Delay from RD Low to INT High CL = 100 pF RL = 1k, CL = 10 pF CL = 100 pF
3
Conditions
Typ (Note 7)
Limit (Note 8) 1.5
Units (Limits) MHz (min) ns (min) ns (max) ns
fs tCONV tAD tS/H tEOC tACC t1H, t0H tINTH
593 20 10 90 10 25 35
560 710
5 400 60 126 20 40 60
ns (min) ns (max) ns (min) ns (max) ns (max) ns (max) ns (max)
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ADC12762
AC Electrical Characteristics
Symbol Parameter
(Continued) The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF-(SENSE) = AGND, and fs = 1.4 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25°C. Conditions Typ (Note 7) Limit (Note 8) -35 -10 15 50 50 20 20 1 Units (Limits) ns (min) ns (max) ns (max) ns (min) ns (min) ns (min) ns (min) µs
tINTL tUPDATE tMS tMH tCSS tCSH tWU
Delay from EOC High to INT Low EOC High to New Data Valid Multiplexer Address Setup Time (MUX Address Valid to EOC Low) Multiplexer Address Hold Time (EOC Low to MUX Address Invalid) CS Setup Time (CS Low to RD Low, S/H Low, or OE High) CS Hold Time (CS High after RD High, S/H High, or OE Low) Wake-Up Time (PD High to First S/H Low)
CL = 100 pF
-25 5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND (GND = AGND = DGND), unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN VCC) the absolute value of current at that pin should be limited to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA and the ambient temperature TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. JA for the V (PLCC) package is 55°C/W. In most cases the maximum derated power dissipation will be reached only during fault conditions. Note 5: Human body model, 100 pF discharged through a 1.5 k resistor. Machine model ESD rating is 200V. Note 6: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: Typicals are at +25°C and represent most likely parametric norm. Note 8: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints. Note 10: Dynamic testing of the ADC12762 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer. Note 11: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation. Note 12: The contributions from the first nine harmonics are used in the calculation of the THD. Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD - 1.76)/6.02. Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby current. Some parts may exhibit significantly higher standby currents than the 50 µA typical. Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
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ADC12762
TRI-STATE Test Circuit and Waveforms
01281102
01281103
01281104
01281105
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