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Details, datasheet, quote on part number:ADC12D040EVAL
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| Part: | ADC12D040EVAL |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | ADC12D040 - Dual 12-Bit, 40 Msps, 600 MW A/D Converter With Internal/external Reference And Sample-and-Hold, Package: Evaluation Board, Pin Nb=- |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC12D040EVAL datasheet File size : 652 kB |
| Request For quote: | Find where to buy ADC12D040EVAL
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Datasheet text preview:
ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and Sample-and-Hold
December 2002
ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and Sample-and-Hold
General Description
The ADC12D040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS), minimum. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. Operating on a single 5V power supply, the ADC12D040 achieves 10.9 effective bits at 10 MHz input and consumes just 600 mW at 40 MSPS, including the reference current. The Power Down feature reduces power consumption to 75 mW. The differential inputs provide a full scale input swing equal to VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. The digital outputs for the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or 2's complement. For ease of interface, the digital output driver power pins of the ADC12D040 can be connected to a separate supply voltage in the range of 2.5V to the digital supply voltage, making the outputs compatible with low voltage systems. When not converting, power consumption can be reduced by pulling the PD pin high, placing the converter into the powerdown state where it typically consumes just 75 mW. The ADC12D040's speed, resolution and single supply operation make it well suited for a variety of applications. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of -40°C to +85°C.
Features
n n n n n n n n n Binary/2's comp output format Single supply operation Internal sample-and-hold Outputs 2.5V to 5V compatible TTL/CMOS compatible input/outputs Low power consumption Power down mode On-chip reference buffer Internal/External 2V reference
Key Specifications
n n n n n n n n n n n n n Resolution Conversion Rate DNL INL SNR (fIN = 10MHz) ENOB (fIN = 10MHz) THD (fIN = 10 MHz) SFDR (fIN = 10 MHz) Data Latency Supply Voltage Power Consumption, Operating Power Down Crosstalk 12 Bits 40 MSPS(min) ± 0.4 LSB(typ) ± 0.7 LSB(typ) 68 dB(typ) 10.9 bits(typ) -78 dB (typ) 80 dB (typ) 6 Clock Cycles +5V ± 5% 600 mW(typ) 75 mW(typ) 80 dB(typ)
Applications
n n n n n n n Ultrasound and Imaging Instrumentation Communications Receivers Sonar/Radar xDSL Cable Modems DSP Front Ends
© 2002 National Semiconductor Corporation
DS200460
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ADC12D040
Connection Diagram
20046001
Ordering Information
Industrial (-40°C TA +85°C) ADC12D040CIVS ADC12D040CIVSX ADC12D040EVAL Package 64 Pin TQFP 64 Pin TQFP Tape and Reel Evaluation Board
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2
ADC12D040
Block Diagram
20046002
3
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ADC12D040
Pin Descriptions and Equivalent Circuits
Pin No. ANALOG I/O 15 2 VINA+ VINB+ Non-Inverting analog signal Inputs. With a 2.0V reference voltage each input signal level is 2.0 VP-P centered on VCM. Inverting analog signal Input. With a 2.0V reference voltage the input signal level is from 2.0 VP-P centered on VCM. This pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. Reference input. This pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. VREF is 2.0V nominal and should be between 1.0V to 2.4V. VREF select pin. With a logic low at this pin the internal 2.0V reference is selected. With a logic high on this pin an external reference voltage should be applied to VREF input pin 7. Symbol Equivalent Circuit Description
16 1
VINA- VINB-
7
VREF
11
INT/EXT REF
13 5
VRPA VRPB
12 6
VRNA VRNB
These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to AGND. DO NOT connect anything else to these pins.
14 4
VRMA VRMB
DIGITAL I/O 60 CLK Digital clock input. The range of frequencies for this input is 100 kHz to 50 MHz (typical) with guaranteed performance at 40 MHz. The input is sampled on the rising edge of this input. OEA and OEB are the output enable pins that, when low, enables their respective TRI-STATE data output pins. When either of these pins is high, the corresponding outputs are in a high impedance state. PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. Output Format pin. A logic low on this pin causes output data to be in straight binary. A logic high on this pin causes the output data to be in 2's complement format.
22 41
OEA OEB
59
PD
21
OF
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ADC12D040
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit
(Continued) Description
24 29 34 39
DA0 DA11 Digital data output pins that make up the 12-bit conversion results of their respective converters. DA0 and DB0 are the LSBs, while DA11 and DB11 are the MSBs of the output word. Output levels are TTL/CMOS compatible.
42 47 52 57
DB0 DB11
ANALOG POWER 9, 18, 19, 62, 63 3, 8, 10, 17, 20, 61, 64 DIGITAL POWER Positive digital supply pin. This pin should be connected to the same quiet +5V source as is VA and be bypassed to DGND with a 0.1 µF monolithic capacitor located within 1 cm of the power pin and with a 10 µF capacitor. The ground return for the digital supply. Positive digital supply pins for the ADC12D040's output drivers. These pins should be connected to a voltage source of +2.5V to +5V and bypassed to DR GND with a 0.1 µF monolithic capacitor. If the supply for these pins are different from the supply used for VA and VD, they should also be bypassed with a 10 µF tantalum capacitor. VDR should never exceed the voltage on VD. All bypass capacitors should be located within 1 cm of the supply pin. The ground return for the digital supply for the ADC12D040's output drivers. These pins should be connected to the system digital ground, but not be connected in close proximity to the ADC12D040's DGND or AGND pins. See Section 5 (Layout and Grounding) for more details. Positive analog supply pins. These pins should be connected to a quiet +5V source and bypassed to AGND with 0.1 µF monolithic capacitors located within 1 cm of these power pins, and with a 10 µF capacitor. The ground return for the analog supply.
VA
AGND
33, 48
VD
32, 49
DGND
30, 51
VDR
23, 31, 40, 50, 58
DR GND
5
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