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Details, datasheet, quote on part number:ADC9708
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| Part: | ADC9708 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => <10 bit |
| Description: | 6-channel 8-bit Microprocessor Compatible A/D Converter (obsolete) |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download ADC9708 datasheet File size : 167 kB |
| Request For quote: | Find where to buy ADC9708
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Datasheet text preview:
ADC9708 6-Channel 8-Bit mP Compatible A D Converter
October 1991
ADC9708 6-Channel 8-Bit mP Compatible A D Converter
General Description
The ADC9708 is a single slope 8-bit 6-channel ADC subsystem that provides all of the necessary analog functions for a microprocessor-based data control system The device uses an external microprocessor system to provide the necessary addressing timing and counting functions and includes a 1-of-8 decoder 8-channel analog multiplexer sample and hold ramp integrator precision ramp reference and a comparator on a single monolithic chip
Y Y
eatures
MPU compatible Excellent linearity over full temperature range g 0 2% maximum Y Typical 300 ms conversion time per channel Y Wide dynamic range includes ground Y Auto-zero and full-scale correction capability Y Ratiometric conversion no precision reference F required Y Single-supply operation Y TTL compatible Y Does not require access to data bus or address bus
Connection Diagram
All Packages
Ordering Information
Commercial (0 C s TA s 70 C) ADC9708CCN ADC9708CCJ Military (b55 C s TA s 125 C) ADC9708CMJ Package N16E J16A Package J16A
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(Top View)
Block Diagram
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C1995 National Semiconductor Corporation TL H 10409 RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Notes 1 2) Pin Temperature Ceramic DIP (Soldering 60 Sec ) Molded DIP (Soldering 10 Sec ) 300 C 260 C 2) 0 C to a 70 C C to a 125 C 4 75V to 15V
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage (VCC) Comparator Output (Ramp Stop) Analog Input Range Digital Input Range Output Sink Current Storage Temperature Range Continuous Total Dissipation (Note 8) Ceramic DIP Package Molded DIP Package ESD Susceptibility (Note 9)
b 65
18V
b 0 3V to a 18V b 0 3V to a 30V b 0 3V to a 30V
Operating Ratings (Notes 1
Operating Temperature Range ADC9708CCN ADC9708CCJ ADC9708CMJ Supply Voltage (VCC) Reference Voltage (VREF) (Note 3) Ramp Capacitor (CH) Reference Current (IR) Analog Input Range Ramp Stop Output Current
10 mA
b 55
C to a 150 C
900 mW 1000 mW TBD
2 8V to 5 25V 300 pF 12 mA to 50 mA 0V to VREF 1 6 mA
Electrical Characteristics
Over recommended operating conditions VCC e 5 0V b55 C s TA s a 125 C for ADC9708CMJ and 0 C s TA s a 70 C for SADC9708CCJ or ADC9708CCN unless otherwise specified ymbol EA ER VOSM tC tA IA tO tM VIH VIL IB IIL IIH IOS IOH VOL PSRR Parameter Conversion Accuracy Linearity Multiplexer Input Offset Voltage Conversion Time per Channel Acquisition Time Acquisition Current ADC9708CCN CCJ ADC9708CMJ Ramp Start Delay Time Multiplexer Address Time Digital Input HIGH Voltage Digital Input LOW Voltage Analog Input Current Input LOW Current Input HIGH Current Input Offset Current Comparator Logic ``1'' Output Leakage Current Comparator Logic ``0'' Output Voltage Power Supply Rejection Ratio Cross Talk between Any Two Channels VOH e 15V IOL e 1 6 mA (Note 6) (Note 7) A0 A1 A2 Ramp Start A0 A1 A2 Ramp Start Channel ON or OFF A0 A1 A2 Ramp Start e 0 4V A0 A1 A2 Ramp Start e 5 5V 10
b1 0 b5
Conditions Over Entire Temperature Range (Note 4) Applies to Any One Channel (Note 5) Channel ON TA e 25 C Channel ON Analog Input e 0V to VREF CH e 300 pF IREF e 50 mA CH e 1000 pF
Typical (Note 10)
g0 2 g 0 08
Limit (Note 11)
g0 3 g0 2
Units (Limit) % (max) % (max) mV (max) mV (max) ms (max) ms (max) mA (min) mA (min) ns ms
20 20 296 20
40 70 350 40 150 115
100 10 20 08
b3 0 b 15
V (min) V mA (min) mA (min) mA (max) mA (max) mA (max) V (max) dB (min) dB (min)
10 30 10 04 40 60
2
Electrical Characteristics
Over recommended operating conditions VCC e 5 0V b55 C s TA s a 125 C for ADC9708CMJ and 0 C s TA s a 70 C for ADC9708CCJ or ADC9708CCN unless otherwise specified (Continued) Symbol ICC CIN COUT Parameter Power Supply Current Input Capacitance Comparator Output Capacitance Conditions VCC e 5V to 15V I0 e 0 Typical (Note 10) 75 30 50 Limit (Note 11) 15 Units (Limit) mA (max) pF pF
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is intended to be functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device N is not operated under the listed test conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 VREF should not exceed VCC b 2V ote 4 Conversion accuracy is defined as the deviations from a straight line drawn between the points defined by channel address 000 (0 scale) and channel N address 111 (full scale) for all channels Note 5 Linearity is defined as the deviation from a straight line drawn between the 0 and full scale points for each channel Note 6 Power supply rejection ratio is defined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel Note 7 Cross Talk between channels e 20 log DVCH D VI
ote 8 Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature is PDmax e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJmax e 150 C and the typical thermal A sistance (iJA) for board mounting follow re DC9708CCN 62 C W ADC9708CCJ ADC9708CMJ 58 C W T te 9 Human body model 100 pF discharged through a 1 5 kX resistor No
iming Diagram
est Circuits
TL H 10409 7
FIGURE 1 Equivalent Timing Waveform for Test Circuits and Applications
Note 10 Typicals are at a 25 C and represent most likely parametric norm ote 11 Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level) Input Timing tA l 400 ms T VREF e IR e TL H 10409 8
2 kX
3 3 kX a 3 3 kX
J 5V
e31
5b31 e 19 mA 100 kX
tR l max e full scale ramp time
e
0 01 c 10b6 c 3 1 e 1 6 ms 19 c 10b6
Note For evaluation purposes the ramp start timing generation can be ima plemented with an LM555 timer (astable operation) or MPU evaluation kit nd a time interval meter for ramp time measurement The TIM meter will measure the time between to 0 to 1 transition of the ramp start and the 1 to 0 transition of the ramp stop The ramp stop is open collector and must F have an external pull-up resistor to VCC
IGURE 2 Slow Speed Evaluation Circuit for Ratiometric Operation 3
Test Circuits (Continued)
ed is selected via address terminals A0 A2 The analog input voltage level is transferred to the external ramp capacitor connected to pin 4 when the input to the ramp start terminal (pin 3) is at a logic 0 (See Figure 1 ) The time to charge the capacitor is the acquisition time which is a function of the output impedance of an amplifier internal to the A D converter and the value of the capacitor After charging the external capacitor the ramp start terminal is switched to a logic 1 which introduces a high impedance between the T analog input voltage and the external capacitor he capacitor begins to discharge at a controlled rate The controlled rate of discharge (ramp) is established by the external reference voltage the external reference resistor the value of the external capacitor and the internal leakage of the A D converter Connected to the capacitor terminal is a comparator internal to the A D converter with its output going to the ramp stop terminal (pin 7) The comparator output is a logic one when the capacitor is charged and switches to a logic 0 when the capacitor is in a discharged state The ramp time is from the time when ramp start goes HIGH (logic ``1'') to when ramp stop goes LOW (logic ``0'') The microprocessor must be programmed to determine this conversion time The ideal (no undesirable internal source impedances leakage paths errors on levels where comparator switches or delay time) conversion time is calculated as follows R CH amp Time e V1 IR Where V1 e Analog Input Voltage Being Measured CH e External Ramp Capacitor VCC b VREF IR e RREF VCC e Power Supply Voltage VREF e Reference Voltage RREF e Reference Resistor
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FIGUC E 3 Linearity Acquisition Time R onversion Time Test Circuit
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FIGURE 4 Static Measurements
Where
Functional Description
6 This Analog to Digital Converter is a single-slope 8-bit -channel A D converter that provides all of the necessary analog functions for a microprocessor-based data control system The device uses the processor system to provide the necessary addressing timing and counting functions and includes a 1-of-8 decoder 8-channel analog multiplexer sample and hold precision current reference ramp inteA grator and comparator on a single monolithic chip pplications that require auto-zero or auto-calibration (See Figures 5 8 ) can use selection of address 000 and 111 for input address lines A0 A2 in conjunction with the arithmetic capability of a microprocessor to provide ground and scaling factors Address 0 0 0 internally connects the input of the ramp generator to ground and may be used for zero offset correction in subsequent conversions Address 1 1 1 internally connects the input of the ramp generator to the voltage reference VREF and may be used for scale factor correction in subsequent conversions For the following reS fer to the Functional Block Diagram ix separate external analog voltage inputs may come into terminals I1 I6 and the specific analog input to be convert-
In actual use the errors due to a nonideal A D converter can be minimized by using a microprocessor to make the calculations (See Figures 5 through 8 ) Channel Selection Input Address Line A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Selected Analog Input Ground I1 I2 I3 I4 I5 I6 VREF
4
Functional Description (Continued)
Auto-Zero and Full-Scale Features
No Zero Offset No Full-Scale Error Count (n) e VIN c 256 VREF
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NF S NZ
i
i
256
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0
(N) has both full-scale and zero errors
FIGURE 5 Ideal Transfer Function
FIGURE 6 Transfer Function with Zero and Full-Scale Error
N e N b NZ N has Full-Scale Error
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N e (N b NZ) c
256 (NF S b NZ)
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FIGURE 7 Transfer Functions with Zero-Correction Added
FIGURE 8 Transfer Function with both Zero and Full-Scale Correction Added 9 2V s VREF s (VCC b 2V) 10 Address lines A0 A1 A2 must be stable throughout the 1 sampling interval tA 1 Pin 6 (RREF) should be bypassed to ground via a 0 02 M mF capacitor icroprocessor Considerations Several alternatives exist from a hardware software stand1 point in microprocessor based systems using the ADC9708 The ramp time measurement may be implemented in software using a register increment followed by a branch 2 back depending on the status of the ramp stop Alternately the ramp stop may be tied into the interrupt structure in systems containing a programmable binary a timer This scheme has the following advantages The CPU is not committed during the ramp time interb val 5 It requires only 5 bits of an I O port for control signals
Typical Applications
Application Suggestions and Formulas 1 The capacitor node impedance is approximately 30 mX and should have no parallel resistance for proper opera2 tion tR when VIN e 0V will be finite (i e the comparator will 3 always toggle for VIN t 0V) The ramp stop output is open collector and an external 4 pull-up resistor is required 5 All digital inputs and outputs are TTL compatible For proper operation timing commences on the 0 to 1 transition of ramp start and terminates on the 1 to 0 tran6 sition of ramp stop tA t CH c VREF (See Figure 1 ) IA b IR
CH C c VIN tR l max e H c VREF 7 tR (ramp time) e IR IR (See Figure 1 ) VCC b VREF 8 IR e RREF
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