|
|
Part: COP884CL
Category:
Description:
Company: National Semiconductor Corporation
Datasheet: Download COP884CL datasheet File size : 8710 kB
Request For quote: Find where to buy COP884CL
Datasheet text preview:
COP688CL COP684CL COP888CL COP884CL COP988CL COP984CL 8-Bit Microcontroller
September 1996
COP688CL COP684CL COP888CL COP884CL COP988CL COP984CL 8-Bit Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology The COP888CL is a member of this expandable 8-bit core processor family of microcontrollers (Continued)
Y
Packages 4 4 PLCC with 40 I O pins 40 DIP with 36 I O pins 28 DIP with 24 I O pins 28 SO with 24 I O pins
CPU Instruction Set Feature
Y Y
Key Features
Y
Y Y
Two 16-bit timers each with two 16-bit registers supporting P rocessor Independent PWM mode External Event counter mode Input Capture mode 4 kbytes of on-chip ROM 128 bytes of on-chip RAM
Y Y Y
Additional Peripheral Features
Y Y Y Y
Idle Timer Multi-input Wake Up (MIWU) with optional interrupts (8) WATCHDOGTM and Clock Monitor logic MICROWIRE PLUSTM serial I O
1 ms instruction cycle time Ten multi-source vectored interrupts servicing External Interrupt with selectable edge Idle Timer T0 Timers (Each with 2 interrupts) MICROWIRE PLUS Multi-Input Wake Up Software Trap Default VIS (default interrupt) Versatile and easy to use instruction set 8-bit Stack Pointer (SP) stack in RAM Two 8-bit Register Indirect Data Memory Pointers (B X)
Fully Static CMOS
Y Y Y
I O Features
Y Y
Y Y
Memory mapped I O Software selectable I O options (TRI-STATE Output Push-Pull Output Weak Pull-Up Input High Impedance Input) High current outputs Schmitt trigger inputs on port G
Low current drain (typically k 1 mA) Single supply operation 2 5V to 6 0V Temperature ranges 0 C to a 70 C b40 C to a 85 C b 55 C to a 125 C
Development Support
Y Y
Emulation and OTP devices Real time emulation and full program debug offered by MetaLink Development System
Block Diagram
TL DD 9766 1
FIGURE 1 Block Diagram
M I-STATE is a registered trademark of National Semiconductor Corporation TR i ICROWIRE PLUSTM M2CMOSTM COPSTM microcontrollers WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation C ceMASTERTM is a trademark of MetaLink Corporation 1996 National Semiconductor Corporation TL DD 9766 RRD-B30M96 Printed in U S A http
www national com
General Description (Continued)
It is a fully static part fabricated using double-metal silicon gate microCMOS technology Features include an 8-bit memory mapped architecture MICROWIRE PLUS serial I O two 16-bit timer counters supporting three modes (Processor Independent PWM generation External Event counter and Input Capture mode capabilities) and two powC er savings modes (HALT and IDLE) both with a multisourced wakeup interrupt capability This multi-sourced interrupt capability may also be used independent of the HALT or IDLE modes Each I O pin has software selectable configurations The device operates over a voltage range of r 2 5V to 6V High throughput is achieved with an efficient egular instruction set operating at a maximum of 1 ms per instruction rate
onnection Diagrams
Plastic Chip Carrier Dual-In-Line Package
TL DD 9766 2
Top View Order Number COP688CL-XXX V COP888CL-XXX V COP988CL-XXX V or COP988CLH-XXX V See NS Plastic Chip Package Number V44A
TL DD 9766 4
Top View Order Number COP688CL-XXX N COP888CL-XXX N COP988CL-XXX N or COP988CLH-XXX N See NS Molded Package Number N40A
Dual-In-Line Package
Order Number COP688CL-XXX N COP884CL-XXX N COP984CL-XXX N or COP984CLH-XXX N See NS Molded Package Number N28B Order Number COP684CL-XXX WM COP884CL-XXX WM COP984CL-XXX WM or COP984CLHXXX WM See NS Surface Mount Package Number M28B
TL DD 9766 5
Top View FIGURE 2 Connection Diagrams
http
www national com
2
Connection Diagrams (Continued)
Pinouts for 28- 40- and 44-Pin Packages L Port I I I I I I I I Type O O O O O O O O Alt Fun MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU INT T1B T1A SO SK SI HALT RESTART Alt Fun 28-Pin Pack 11 12 13 14 15 16 17 18 25 26 27 28 1 2 3 4 19 20 21 22 7 8 40-Pin Pack 17 18 19 20 21 22 23 24 35 36 37 38 3 4 5 6 25 26 27 28 9 10 11 12 13 14 44-Pin Pack 17 18 19 20 25 26 27 28 39 40 41 42 3 4 5 6 29 30 31 32 9 10 11 12 13 14 15 16 33 34 35 36 43 44 1 2 21 22 23 24
0 L1 L2 L3 L4 L5 L6 L7 G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 I0 I1 I2 I3 I4 I5 I6 I7 D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 Unused Unused VCC GND CKI RESET
T2A T2B
IO WDOUT IO IO IO IO I I CKO O O O O I I I I I I I I O O O O I I I I I I I I O O O O O O O O
9 10
29 30 31 32 39 40 1 2
6 23 5 24
16 15 8 33 7 34
8 37 7 38
h
e On the 40-pin package Pins 15 and 16 must be connected to GND
3
ttp
www national com
Absolute Maximum Ratings
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications upply Voltage (VCC) Voltage at Any Pin D Total Current into V
CC Pin (Source)
Total Current out of GND Pin (Sink) Storage Temperature Range
b 65
110 mA
C to a 140 C
7V
b 0 3V to VCC a 0 3V
100 mA
Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings 0 C s TA s a 70 C unless otherwise specified Min 25 40 Typ Max 40 60 0 1 VCC 12 5 25
k0 7 k0 4
C Electrical Characteristics COP98XCL
Parameter Operating Voltage COP98XCL COP98XCLH Power Supply Ripple (Note 1) Supply Current (Note 2) CKI e 10 MHz CKI e 4 MHz HALT Current (Note 3) IDLE Current CKI e 10 MHz Input Levels RESET Logic High Logic Low CKI (External and Crystal Osc Modes) Logic High Logic Low All Other Inputs Logic High Logic Low Hi-Z Input Leakage Input Pullup Current G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) VCC e 6V Peak-to-Peak
Conditions
Units V V V mA mA mA mA mA
VCC e 6V tc e 1 ms VCC e 4V tc e 2 5 ms VCC e 6V CKI e 0 MHz VCC e 4V CKI e 0 MHz VCC e 6V tc e 1 ms
8 5 35
0 8 VCC 0 2 VCC 0 7 VCC 0 2 VCC 0 7 VCC 0 2 VCC
b1 b 40 a1 b 250
V V V V V V mA mA V
VCC e 6V VIN e 0V
0 35 VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
e e e e e e e e e e
4V VOH e 3 3V 2 5V VOH e 1 8V 4V VOL e 1V 2 5V VOL e 0 4V 4V VOH e 2 7V 2 5V VOH e 1 8V 4V VOH e 3 3V 2 5V VOH e 1 8V 4V VOL e 0 4V 2 5V VOL e 0 4V
b0 4 b0 2
10 20
b 10 b2 5 b0 4 b0 2 b 100 b 33
mA mA mA mA mA mA mA mA mA mA
16 07
Note 1 Rate of voltage change must be less then 0 5 V ms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open h ote 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Test conditions All inputs tied to VCC L and G0 G5 configured as outputs and set high The D port set to zero The clock monitor is disabled
ttp
www national com
4
DC Electrical Characteristics 0 C s TA s a 70 C unless otherwise specified (Continued)
Parameter TRI-STATE Leakage Allowable Sink Source Current per Pin D Outputs (Sink) All others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage Vr Input Capacitance Load Capacitance on D2 TA e 25 C 500 ns Rise and Fall Time (Min) Conditions VCC e 6 0V Min
b1
Typ
Max
a1
Units mA
15 3
g 100
mA mA mA V
2 7 1000
pF pF
AC Electrical Characteristics 0 C s TA s a 70 C unless otherwise specified
Parameter Instruction Cycle Time (tc) Crystal or Resonator R C Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note 5) tPD1 tPD0 SO SK All Others MICROWIRETM Setup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time Reset Pulse Width Conditions 4V s VCC s 6V 2 5V s VCC k 4V 4V s VCC s 6V 2 5V s VCC k 4V 4V s VCC s 6V 2 5V s VCC k 4V 4V s VCC s 6V 2 5V s VCC k 4V RL e 2 2k CL e 100 pF 4V s VCC s 6V 2 5V s VCC k 4V 4V s VCC s 6V 2 5V s VCC k 4V 20 56 220 1 1 1 1 1 07 1 75 1 25 ms ms ms ms ns ns ns tc tc tc tc ms Min 1 25 3 75 200 500 60 150 Typ Max DC DC DC DC Units ms ms ms ms ns ns ns ns
Note 4 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective N sistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V re ote 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs h
5
ttp
www national com
Others parts begin by co
CO-1 CO-2 CO-3 CO-4 CO-5 CO-6
|
|
|
