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Details, datasheet, quote on part number:DAC1222LC
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| Part: | DAC1222LC |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => 10-14 bit |
| Description: | 12-bit Binary Multiplying D/A Converter (discontinued) |
| Company: | National Semiconductor Corporation |
| Datasheet: | Download DAC1222LC datasheet File size : 271 kB |
| Request For quote: | Find where to buy DAC1222LC
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Datasheet text preview:
DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying D A Converter DAC1220 DAC1222 12-Bit Binary Multiplying D A Converter
May 1996
DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying D A Converter DAC1220 DAC1222 12-Bit Binary Multiplying D A Converter
General Description
The DAC1020 and the DAC1220 are respectively 10 and 12-bit binary multiplying digital-to-analog converters A deposited thin film R-2R resistor ladder divides the reference current and provides the circuit with excellent temperature tracking characteristics (0 0002% C linearity error temperature coefficient maximum) The circuit uses CMOS current switches and drive circuitry to achieve low power consumpT tion (30 mW max) and low output leakages (200 nA max) he digital inputs are compatible with DTL TTL logic levels as well as full CMOS logic level swings This part combined with an external amplifier and voltage reference can be used as a standard D A converter however it is also very attractive for multiplying applications (such as digitally controlled gain blocks) since its linearity error is essentially independent of the voltage reference All inputs are protected from damage due to static discharge by diode clamps to V a T and ground his part is available with 10-bit (0 05%) 9-bit (0 10%) and 8-bit (0 20%) non-linearity guaranteed over temperature D (note 1 of electrical characteristics) The DAC1020 AC1021 and DAC1022 are direct replacements for the 10bit resolution AD7520 and AD7530 and equivalent to the AD7533 family The DAC1220 and DAC1222 are direct replacements for the 12-bit resolution AD7521 and AD7531 Fmily fa
eatures
Y Y Y Y Y Y Y Y Y Y
Linearity specified with zero and full-scale adjust only Non-linearity guaranteed over temperature Integrated thin film on CMOS structure 10-bit or 12-bit resolution Low power dissipation 10 mW 15V typ Accepts variable or fixed reference b25VsVREFs25V 4-quadrant multiplying capability Interfaces directly with DTL TTL and CMOS Fast settling time 500 ns typ Low feedthrough error LSB 100 kHz typ
Equivalent Circuit
Note Switches shown in digital high state
TL H 5689 1
Ordering Information
Temperature Range NonLinearity 0 05% 0 10% 0 20% Package Outline Temperature Range NonLinearity 0 05% 0 20% DAC1220LCN DAC1222LCN DAC1020LCN DAC1021LCN DAC1022LCN
10-BIT D A CONVERTERS 0 C to 70 C AD7520LN AD7530LN AD7520KN AD7530KN AD7520JN AD7530JN N16A 12-BIT D A CONVERTERS 0 C to 70 C AD7521LN AD7531LN AD7521JN AD7531JN N18A
b 40 b 40
C to 85 C
DAC1020LCV
DAC1020LIV
V20A
C to a 85 C
AD7521LD AD7531LD AD7521JD AD7531JD J18A
DAC1220LCJ DAC1222LCJ
Package Outline
C Note Devices may be ordered by either part number
1996 National Semiconductor Corporation
TL H 5689
RRD-B30M96 Printed in U S A
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Absolute Maximum Ratings (Note 5)
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales V Office Distributors for availability and specifications
a
Operating Ratings
Min Temperature (TA) DAC1020LIV DAC1220LCJ DAC1222LCJ DAC1020LCN DAC1020LCV DAC1021LCN DAC1022LCN DAC1220LCN DAC1222LCN Max Units
to Gnd
17V
g 25V
b 40
a 85 a 70 a 70 a 70
C C C C
VREF to Gnd Digital Input Voltage Range DC Voltage at Pin 1 or Pin 2 (Note 3) Storage Temperature Range Lead Temperature (Soldering 10 sec ) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic) ESD Susceptibility (Note 4)
V a to Gnd
b 100 mV to V a b 65
C to a 150 C
260 C 300 C 800V
0 0 0
Electrical Characteristics (V a e 15V
Parameter Conditions
VREF e 10 000V TA e 25 C unless otherwise specified) DAC1020 DAC1021 DAC1022 Min Typ Max DAC1220 DAC1222 Min 12 Typ Max Bits Units
Resolution Linearity Error TMINkTAkTMAX b ( 10VkVREFk a 10V Note 1) End Point Adjustment Only (See Linearity Error in Definition of Terms) DAC1020 DAC1220 DAC1021 DAC1022 DAC1222
b 10V s VREF s a 10V (Notes 1 and 2) b 10V s VREF s a 10V (Notes 1 and 2)
10
10-Bit Parts 9-Bit Parts 8-Bit Parts Linearity Error Tempco Full-Scale Error Full-Scale Error Tempco Output Leakage Current IOUT 1 IOUT 2 Power Supply Sensitivity
0 05 0 10 0 20 0 0002 03 10 0 001 03
0 05 0 10 0 20 0 0002 10 0 001
% FSR % FSR % FSR % FS C % FS % FS C
TMINkTAkTMAX (Note 2) TMINsTAsTMAX All Digital Inputs Low All Digital Inputs High All Digital Inputs High ( 4VsV a s16V (Note 2) 1 Figure 2) 10 RL e 100X from 0 to 99 95% FS All Digital Inputs Switched Simultaneously All Digital Inputs Low VREF e 20 Vp-p 100 kHz J Package (Note 4) N Package All Digital Inputs Low All Digital Inputs High All Digital Inputs Low All Digital Inputs High 0 005
200 200 0 005
200 200
nA nA % FS V
VREF Input Resistance Full-Scale Current Settling Time
15
20
10
15
20
kX
500 10 6 2 40 200 200 40 9 5
500 10 6 2 40 200 200 40 9 5
ns mVp-p mVp-p mVp-p pF pF pF pF
VREF Feedthrough
Output Capacitance IOUT 1 IOUT 2
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2
Electrical Characteristics
Parameter
(V a e 15V VREF e 10 000V TA e 25 C unless otherwise specified) (Continued) DAC1020 DAC1021 DAC1022 Min Typ Max 08 24 1
b 50
Conditions
DAC1220 DAC1222 Min Typ Max 08 24
Units
Digital Input Low Threshold High Threshold Digital Input Current
(Figure 1) TMINkTAkTMAX TMINkTAkTMAX
TMINsTAsTMAX Digital Input High Digital Input Low All Digital Inputs High All Digital Inputs Low
V V mA mA mA mA V
100
b 200
1
b 50
100
b 200
Supply Current Operating Power Supply Range
02 06 5
16 2 15 5
02 06
16 2 15
(Figures 1 and 2)
Note 1 VREF e g 10V and VREF e g 1V A linearity error temperature coefficient of 0 0002% FS for a 45 C rise only guarantees 0 009% maximum change in linearity error For instance if the linearity error at 25 C is 0 045% FS it could increase to 0 054% at 70 C and the DAC will be no longer a 10-bit part Note however that the linearity error is specified over the device full temperature range which is a more stringent specification since it includes the linearity error N temperature coefficient Note 2 Using internal feedback resistor as shown in Figure 3 0 ote 3 Both IOUT 1 and IOUT 2 must go to ground or the virtual ground of an operational amplifier If VREF e 10V every millivolt offset between IOUT 1 or IOUT 2 N 005% linearity error will be introduced Note 4 Human body model 100 pF discharged through a 1 5 kX resistor ote 5 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating N the device beyond its specified operating conditions ote 6 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX iJA and the ambient temepature TA The maximum allowable power dissipation at any temperature is PD e (TJMAX b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJMAX e 125 C and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85 C W For the N18 package iJA is 120 C W for the N16 this number is 125 C W and for the V20 this number is 95 C W
Typical Performance Characteristics
TL H 5689 2
FIGURE 1 Digital Input Threshold vs Ambient Temperature
FIGURE 2 Gain Error Variation vs V a
3
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Typical Applications
The following applications are also valid for 12-bit systems O using the DAC1220 and 2 additional digital inputs perational Amplifier Bias Current (Figure 3 ) The op amp bias current Ib flows through the 15k internal feedback resistor BI-FET op amps have low Ib and therefore the 15k c Ib error they introduce is negligible they are V strongly recommended for the DAC1020 applications
OS Considerations The output impedance ROUT of the DAC is modulated by the digital input code which causes a modulation of the operational amplifier output offset It is therefore recommended to adjust the op amp VOS ROUT is E 15k if more than 4 digital inputs are high ROUT is E 45k if a single digital input is high and ROUT approaches infinity if all inputs are low
perational Amplifier VOS Adjust (Figure 3 ) Connect all digital inputs A1 A10 to ground and adjust the potentiometer to bring the op amp VOUT pin to within g 1 mV from ground potential If VREF is less than 10V a finer VOS adjustment is required It is helpful to increase the resolution of the VOS adjust procedure by connecting a 1 kX resistor between the inverting input of the op amp to g Fround After VOS has been adjusted remove the 1 kX ull-Scale Adjust (Figure 4 ) Switch high all the digital inputs A1 A10 and measure the op amp output voltage Use a 500X potentiometer as shown to bring ll VOUT ll to a voltage equal to VREF c 1023 1024 O
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER Op Amp Family LF357 LF356 LF351 LM741 CF 10 pF 22 pF 24 pF 0 Ri 2 4k % % % P 25k 25k 10k 10k VW Va Va Vb Vb Circuit Settling Time ts 1 5 ms 3 ms 4 ms 40 ms Circuit Small Signal BW 1M 0 5M 0 5M 200 kHz
TL H 5689 3
VOUT e b VREF
b 10V s VREF s 10V
A1 A2 A3 A10 a a a 2 4 8 1024
J
0 s VOUT s b
1023 VREF 1024
where AN e 1 if the AN digital input is high AN e 0 if the AN digital input is low
FIGURE 3 Basic Connection Unipolar or 2-Quadrant Multiplying Configuration (Digital Attenuator)
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4
Typical Applications (Continued)
FIGURE 4 Full-Scale Adjust
FIGURE 5 Alternate Full-Scale Adjust (Allows Increasing or Decreasing the Gain)
VOUT 1 e b VREF VOUT2 e VREF
where VREF can be an AC signal
2
A1
2
A1
a
A2 A3 A10 a a 4 8 1024
a
A2 A3 A10 a a 4 8 1024
J 2
c
J
TL H 5689 4
B1
a
B2 B3 B10 a a 4 8 1024
J
FIGURE 6 Precision Analog-to-Digital Multiplier
5
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