|Category||Interface and Interconnect => LVDS (Low Voltage Differential Signaling) => Bus LVDS Serializer / Deserializer Devices|
|Title||Bus LVDS Serializer / Deserializer Devices|
|Description||DS92LV1021A - 16 MHZ - 40 MHZ 10-Bit Serializer, Package: SSOP-EIAJ, Pin Nb=28|
|Company||National Semiconductor Corporation|
|Datasheet||Download DS92LV1021AMSAX datasheet
|Cross ref.||Similar parts: DS92LV1021AMSA/NOPB, SN65LV1021DB, DS92LV1023E, SN65LV1023A, SN65LV1023A-EP, SN65LV1224B-EP|
The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1021A can transmit data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits both clock and data bits serially, it eliminates clockto-data and data-to-data skew. The powerdown pin saves power by reducing supply current when the device is not being used. Upon power up of the Serializer, you can choose to activate synchronization mode or use one of National Semiconductor's Deserializers in the synchronization-torandom-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the DS92LV1021A output pins into TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.Features
Guaranteed transition every data transfer cycle Single differential pair eliminates multi-channel skew Flow-through pinout for easy PCB layout 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) 10-bit parallel interface for 1 byte data plus 2 control bits Programmable edge trigger on clock Bus LVDS serial output rated for 27 load Small 28-lead SSOP package-MSATRI-STATE is a registered trademark of National Semiconductor Corporation.
The is an upgrade to the DS92LV1021. The DS92LV1021A no longer has a power-up sequence requirement. Like the DS92LV1021, the a 10-bit Serializer designed to transmit data over a differential backplane at clock speeds from 40MHz. It may also be used to drive data over Unshielded Twisted Pair (UTP) cable. The DS92LV1021A can be used with any of National's 10-bit BLVDS Deserializers (DS92LV1212A for example) and has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE. The following sections describe each active and passive state.
low selects the falling edge. If either of the SYNC inputs is high for 5*TCLK cycles, the data DIN0-DIN9 is ignored regardless of the clock edge. A start bit and a stop bit, appended internally, frame the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. Serialized data and clock bits (10+2 bits) are transmitted from the serial data output (DO at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate = 480 Mega bits per second. Since only 10 bits are from input data, the serial "payload" rate is ten times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate = 400 Mbps. TCLK is provided by the data source and must be in the range of 16 MHz to 40 MHz nominal. The outputs (DO ± ) can drive a backplane or a point-to-point connection. The outputs transmit data when the enable pin (DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are low. The DEN pin may be used to TRI-STATE the outputs when driven low.
Before data can be transferred, the Serializer must be initialized. Initialization refers to synchronization of the Serializer's PLL to a local clock. When VCC is applied to the Serializer, the outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.5V) the Serializer's PLL begins locking to the local clock. The local clock is the transmit clock, TCLK, provided by the source ASIC or other device. Once the PLL locks to the local clock, the Serializer is ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs. The SYNC pattern is composed of six ones and six zeros switching at the input clock rate. Control of the SYNC pins is left to the user. One recommendation is a direct feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low.
The ideal crossing point is the best case start and stop point for a normalized bit. Each ideal crossing point is found by dividing the clock period by twelve--two clock bits plus ten data bits. For example, a 40 MHz clock has a period of 25ns. The 25ns divided by 12 bits is approximately 2.08ns. This means that each bit width is approximately 2.08ns, and the ideal crossing points occur every 2.08ns. For a graphical representation, please see Figure 9.
The Deserializer LOCK pin driven low indicates that the Deserializer PLL is locked to the embedded clock edge. If the Deserializer loses lock, the LOCK output will go high and the outputs (including RCLK) will be TRI-STATE. The LOCK pin must be monitored by the system to detect a loss of synchronization, and the system must decide it is necessary to pulse the Serializer or SYNC2 pin to resynchronize. There are multiple approaches possible. One recommendation is to provide a feedback loop using the
After initialization, the Serializer inputs DIN0DIN9 may be used to input data to the Serializer. Data is clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the TCLK_R/F pin. TCLK_R/F high selects the rising edge for clocking data and
LOCK pin itself to control the sync request of the Serializer SYNC2). At the time of publication, other than the DS92LV1210, all other Deserializers from National Semiconductor have random lock capability. This feature does not require the system user to send SYNC patterns upon loss of lock. However, lock times can only be guaranteed with transmission of SYNC patterns. Dual SYNC pins are provided for multiple control in a multi-drop application.
Powerdown, the PLL stops and the outputs go into TRISTATE, disabling load current and reducing supply current into the milliamp range. To exit Powerdown, PWRDN must be driven high. Both the Serializer and Deserializer must reinitialize and resynchronize before data can be transferred. The Deserializer will initialize and assert LOCK high until it is locked to the Bus LVDS clock.
For the Serializer, TRI-STATE is entered when the DEN pin is driven low. This will TRI-STATE both driver output pins (DO+ and DO-). When DEN is driven high, the serializer will return to the previous state as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when no data is being transferred. The device enters Powerdown when the PWRDN pin is driven low on the Serializer. InOrder Number NSID DS92LV1021AMSA Function Serializer Package MSA28
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