|Category||Interface and Interconnect => LVDS (Low Voltage Differential Signaling) => Bus LVDS Serializer / Deserializer Devices|
|Title||Bus LVDS Serializer / Deserializer Devices|
|Description||DS92LV1021 - 16 MHZ - 40 MHZ 10-Bit Serializer, Package: Evaluation Board, Pin Nb=-|
|Company||National Semiconductor Corporation|
|Datasheet||Download DS92LV1021TMSA datasheet
|Cross ref.||Similar parts: DS92LV1021AMSA/NOPB, SN65LV1021DB, DS92LV1212A, DS92LV1023E, SN65LV1023A-EP, SN65LV1224B-EP|
The DS92LV1021 transforms a 10-bit wide parallel CMOS/ TTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1210 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and separates clock. The DS92LV1021 may transmit data over heavily loaded backplanes or 10 meters of cable. The reduced cable, PCB trace count and connector size saves cost and makes PCB design layout easier. Clock-to-data and data-to-data skew are eliminated since one output will transmit both clock and all data bits serially. The powerdown pin is used to save power, by reducing supply current when either device is not in use. The Serializer has a synchronization mode that should be activated upon power-up of the device. The Deserializer will establish lock to this signal within 1024 cycles, and will flag Lock status. The embedded clock guarantees a transition on the bus every 12-bit cycle; eliminating transmission errors due to charged cable conditions. The DS92LV1021 output pins may be TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.Features
Guaranteed transition every data transfer cycle Single differential pair eliminates multi-channel skew Flow-through pinout for easy PCB layout 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) 10-bit parallel interface for 1 byte data plus 2 control bits Synchronization mode and LOCK indicator Programmable edge trigger on clock High impedance on receiver inputs when power is off Bus LVDS serial output rated for 27 load Small 28-lead SSOP package-MSATRI-STATE is a registered trademark of National Semiconductor Corporation.
The DS92LV1021 and a 10-bit Serializer / Deserializer chipset designed to transmit data over a heavily loaded differential backplanes at clock speeds from 40MHz. It may also be used to drive data over Unshielded Twisted Pair (UTP) cable. The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE The following sections describe each operation and passive state.
Control of the sync pins is left to the user. A feedback loop between the LOCK pin is one recommendation. Another option is that one or both of the Serializer SYNC inputs are asserted for at least 1024 cycles of TCLK to initiate transmission of SYNC patterns. The Serializer will continue to send SYNC patterns after the minimum 1024 if either of the SYNC inputs remain high. When the Deserializer detects edge transitions at the Bus LVDS input it will attempt to lock to the embedded clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low the Deserializer outputs represent incoming Bus LVDS data.
Before data can be transferred both devices must be initialized. Initialization refers to synchronization of the Serializer and the Deserializer PLL's to local clocks that may be the same or separate. Afterward, synchronization of Deserializer to Serializer occurs as the second step of initialization. Step 1: When VCC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE ® and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.5V) the PLL in each device begins locking to a local clock. For the Serializer, the local clock is the transmit clock, TCLK, provided by the source ASIC or other device. For the Deserializer, the local clock is provided by an on-board oscillator or other source and applied to the REFCLK pin. After VCC OK is reached the device's PLL will lock. The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. The Serializer is now ready to send data or SYNC patterns depending on the levels of the SYNC1 and SYNC2 inputs. The SYNC pattern is composed of six ones and six zeros switching at the input clock rate. The Deserializer LOCK output will remain high while its PLL is locking to the local clock- the REFCLK input and then to SYNC patterns on the input. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The transmission of SYNC patterns to the Deserializer enables the Deserializer to lock to the Serializer signal.
After initialization, the Serializer inputs DIN0DIN9 may be used to input data to the Serializer. Data is clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe in data is selectable via the TCLK_R/F pin. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC inputs is high for 5*TCLK cycles the data at DIN 0-DIN9 is ignored regardless of the clock edge. A start bit and a stop bit, appended internally, frame the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. Serialized data and clock bits (10+2 bits) are transmitted from the serial data output (DO) at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate = 480 Mega bits per second. Since only 10 bits are from input data, the serial "payload" rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate = 400 Mbps. TCLK is provided by the data source and must be in the range 16 MHz to 40 MHz nominal. The outputs (DO ± ) can drive a heavily loaded backplane or a point-to-point connection. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high and SYNC1 and SYNC2 are low. The DEN pin may be used to TRISTATE the outputs when driven low. The LOCK pin on the Deserializer is driven low when it is synchronized with the Serializer. The Deserializer locks to
the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0ROUT9 is invalid. RCLK pin is the reference to data on the ROUT0-ROUT9 pins. The polarity of the RCLK edge is controlled by the RCLK_R/F input. ROUT(0-9), LOCK and RCLK outputs will drive a minimum of three CMOS input gates (15 pF load) with 40 MHz clock.
there is no data to be transferred. Powerdown is entered when PWRDN and REN are driven low on the Deserializer, and when the PWRDN is driven low on the Serializer. In Powerdown, the PLL is stopped and the outputs go into TRI-STATE, disabling load current and also reducing supply current to the milliamp range. To exit Powerdown, PWRDN is driven high. Both the Serializer and Deserializer must reinitialize and resynchronize before data can be transferred. Initialization of the Serializer takes 1024 TCLK cycles. The Deserializer will initialize and assert LOCK high until it is locked to the Bus LVDS clock.
The Deserializer LOCK pin driven low indicates that the Deserializer PLL is locked to the embedded clock edge. If the Deserializer loses lock, the LOCK output will go high and the outputs (including RCLK) will be TRI-STATE. The LOCK pin must be monitored by the system to detect a loss of synchronization and the system must arrange to pulse the Serializer or SYNC2 pin to resynchronize. There are multiple approaches possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer or SYNC2). Otherwise, LOCK pin needs to be monitored and when is a high, the system needs to ensure that one or both of the Serializer SYNC inputs area asserted for at least 1024 cycles of TCLK. A minimum of 1024 sync patterns are needed to resynchronize. Dual SYNC pins are provided for multiple control in a multi-drop application.
For the Serializer, TRI-STATE is entered when the DEN pin is driven low. This will TRI-STATE both driver output pins (DO+ and DO-). When DEN is driven high the serializer will return to the previous state as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). For the Deserializer, TRI-STATE is entered when the REN pin is driven low. This will TRI-STATE the receiver output pins (ROUT0ROUT9), LOCK and RCLK. Order Numbers NSID DS92LV1021TMSA DS92LV1210TMSA Function Serializer Deserializer Package MSA28
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when
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