Details, datasheet, quote on part number: DS92LV1023
PartDS92LV1023
CategoryInterface and Interconnect => LVDS (Low Voltage Differential Signaling)
Description40 MHz-66MHz 10-Bit Serializer
The DS92LV1023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1224 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. The DS92LV1023 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the DS92LV1023 output pins into TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 40 MHz and 66 MHz.


Features
Clock recovery from PLL lock to random data patterns.
Guaranteed transition every data transfer cycle
Chipset (Tx + Rx) power consumption < 500 mW (typ) @ 66 MHz
Single differential pair eliminates multi-channel skew
Flow-through pinout for easy PCB layout
660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
10-bit parallel interface for 1 byte data plus 2 control bits
Synchronization mode and LOCK indicator
Programmable edge trigger on clock
High impedance on receiver inputs when power is off
Bus LVDS serial output rated for 27 load
Small 28-lead SSOP package
CompanyNational Semiconductor Corporation
DatasheetDownload DS92LV1023 datasheet
Cross ref.Similar parts: MAX9207
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Features, Applications

The DS92LV1023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1224 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. The DS92LV1023 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the DS92LV1023 output pins into TRI-STATE ® to achieve a high impedance state. The PLL can lock to frequencies between 40 MHz and 66 MHz.

Features

n Clock recovery from PLL lock to random data patterns. n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption 500 mW (typ) @ 66 MHz n Single differential pair eliminates multi-channel skew n Flow-through pinout for easy PCB layout n 660 Mbps serial Bus LVDS data rate (at 66 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits n Synchronization mode and LOCK indicator n Programmable edge trigger on clock n High impedance on receiver inputs when power is off n Bus LVDS serial output rated for 27 load n Small 28-lead SSOP package

TRI-STATE is a registered trademark of National Semiconductor Corporation.

The DS92LV1023 and DS92LV1224 are a 10-bit Serializer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from to 66 MHz. The chipset is also capable of driving data over Unshielded Twisted Pair (UTP) cable. The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE The following sections describe each operation and passive state.

The user's application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after both SYNC inputs return low. When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low, the Deserializer outputs represent incoming Bus LVDS data.

After initialization, the Serializer will accept data from inputs DIN0­DIN9. The Serializer uses the TCLK input to latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC inputs is high for 5*TCLK cycles, the data DIN0-DIN9 is ignored regardless of clock edge. After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO at 12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate = 792 Mega-bits-per-second. Since only 10 bits are from input data, the serial "payload" rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz, the payload data rate = 660 Mbps. The data source provides TCLK and must be in the range of 40 MHz to 66 MHz nominal. The Serializer outputs (DO ± ) can drive a point-to-point connection or in limited multi-point or multi-drop backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE. When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the embedded

Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of the Serializer and Deserializer PLL's to local clocks, which may be the same or separate. Afterwards, synchronization of the Deserializer to Serializer occurs. Step 1: When you apply VCC to both Serializer and/or Deserializer, the respective outputs enter TRI-STATE ® , and on-chip power-on circuitry disables internal circuitry. When VCC reaches VCCOK (2.5V) the PLL in each device begins locking to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin. The Serializer outputs remain in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer is now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs or a data stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the input clock rate. Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC patterns on the input. Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock to the Serializer signal within a specified time. See Figure 9.

clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0­ROUT9 is invalid. The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled by the RCLK_R/F input. See Figure 13. ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 66 MHz clock.

When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the Deserializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter TRI-STATE. The user's system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can arrange to pulse the Serializer or SYNC2 pin to resynchronize. Multiple resynchronization approaches are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are critical. However, the Deserializer can lock to random data, which is discussed in the next section.

low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the Deserializer could become locked to the data pattern rather than the clock. Circuitry within the DS92LV1224 can detect that the possibility of "false lock" exists. The circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming active until the potential "false lock" pattern changes. The false lock detect circuitry expects the data will eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock bits in the serial data stream. Graphical representations of RMT are shown in Figure 1. Please note that RMT only applies to bits DIN0-DIN8.

When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In Powerdown, the PLL stops and the outputs enterTRI-STATE, which disables load current and reduces supply current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high. Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and assert LOCK high until lock to the Bus LVDS clock occurs.

The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer. However, the DS92LV1224 can attain lock to a data stream without requiring the Serializer to send special SYNC patterns. This allows the DS92LV1224 to operate in "open-loop" applications. Equally important is the Deserializer's ability to support hot insertion into a running backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time. However, please see Table 1 for some general random lock times under specific conditions. The primary constraint on the "random" lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up. As described in the next paragraph, the data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the Deserializer could enter "false lock" - falsely recognizing the data pattern as the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN 9, is held at a

The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and DO-) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0­ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. TABLE 1. Random Lock Times for the DS92LV1224 40 MHz Maximum Mean Minimum Conditions: MHz 3.0 0.43 Units µS

1) Difference in lock times are due to different starting points in the data pattern with multiple parts.


 

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