Details, datasheet, quote on part number: DS92LV1212
PartDS92LV1212
CategoryInterface and Interconnect => Line Drivers => LVDS Specific
TitleLVDS Specific
Description16 MHZ
CompanyNational Semiconductor Corporation
DatasheetDownload DS92LV1212 datasheet
Quote
Find where to buy
 
  

 

Features, Applications
DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

The is an upgrade of the DS92LV1210. It maintains all of the features of the DS92LV1210 with the additional capability of locking to the incoming data stream without the need of SYNC patterns. This makes the DS92LV1212 useful in applications where the Deserializer must be operated "open-loop" without a feedback path from the Deserializer to the Serializer. The DS92LV1212 is designed to be used with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212 receives a Bus LVDS serial data stream and transforms it into a 10-bit wide parallel data bus and separate clock. The reduced cable, PCB trace count and connector size saves cost and makes PCB layout easier. Clock-to-data and data-to-data skews are eliminated since one input receives both clock and data bits serially. The powerdown pin is used to save power by reducing the supply current when the device is not in use. The Deserializer will establish lock to a synchronization pattern within specified lock times but it can also lock to a data stream without SYNC patterns.

Features

n Clock recovery without SYNC patterns-random lock n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption < 300mW (typ) 40MHz n Single differential pair eliminates multi-channel skew n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits or UTOPIA I Interface n Synchronization mode and LOCK indicator n Flow-through pinout for easy PCB layout n High impedance on receiver inputs when power is off n Programmable edge trigger on clock n Footprint compatible with DS92LV1210 n Small 28-lead SSOP package-MSA

TRI-STATE is a registered trademark of National Semiconductor Corporation.

The a 10-bit Deserializer chip designed to receive data over a heavily loaded differential backplanes at clock speeds from 16 MHz to 40 MHz. It may also be used to receive data over Unshielded Twisted Pair (UTP) cable. The chip has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE The following sections describe each operation and passive state.

formation. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low the Deserializer outputs represent incoming Bus LVDS data.

Serialized data and clock bits (10+2 bits) are received at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate = 480 Mega bits per second. Since only 10 bits are from input data, the serial "payload" rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate = 400 Mbps. TCLK is provided by the data source and must be in the range 16 MHz to 40 MHz nominal. The LOCK pin on the Deserializer is driven low when it is synchronized with the Serializer. The Deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0­ROUT9 is invalid. RCLK pin is the reference to data on the ROUT0-ROUT9 pins. The polarity of the RCLK edge is controlled by the RCLK_R/F input. ROUT(0-9), LOCK and RCLK outputs will drive a minimum of three CMOS input gates (15 pF load) with 40 MHz clock.

Before data can be transferred the Deserializer must be initialized. The Deserializer should be powered up with the PWRDN pin held low. After VCC stabilizes the PWRDN pin can be forced high. The Deserializer is ready to lock to the incoming data stream. Step 1: When VCC is applied to the Deserializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.5V) the PLL is ready to lock to incoming data or synchronization patterns. The local clock is applied to the REFCLK pin. The Deserializer LOCK output will remain high while its PLL is locking to the incoming data or to SYNC patterns on the input. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The Deserializer will lock to non-repetitive data patterns, however, the transmission of SYNC patterns to the Deserializer enables the Deserializer to lock to the Serializer signal within a specified time. Control of the Serializer SYNC1/2 pins is left to the user. A feedback loop between the LOCK pin is one recommendation. Another option is that one or both of the Serializer SYNC inputs are asserted for at least 1024 cycles of TCLK to initiate transmission of SYNC patterns. The Serializer will continue to send SYNC patterns after the minimum 1024 if either of the SYNC inputs remain high. When the Deserializer detects edge transitions at the Bus LVDS input it will attempt to lock to the embedded clock in-

The Deserializer LOCK pin driven low indicates that the Deserializer PLL is locked to the embedded clock edge. If the Deserializer loses lock, the LOCK output will go high and the outputs (including RCLK) will be TRI-STATE. The LOCK pin must be monitored by the system to detect a loss of synchronization. The system can arrange to pulse the Serializer or SYNC2 pin to resynchronize. There are multiple approaches possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer SYNC2). A minimum of 1024 sync patterns are needed to resynchronize. Dual SYNC pins are provided for multiple control in a multi-drop application.

The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer, however, the DS92LV1212 can attain lock to a data stream without requiring special SYNC patterns to be sent by the Serializer. This allows the to be used in applications where the Deserializer must operate "open-loop" and supports hot insertion into a running backplane. Because the data stream is essentially random the time for the DS92LV1212 to attain lock is variable and cannot be predicted. The primary constraint on the "random" lock time is the initial phase relation when the Deserializer is powered up. The data contained in the data stream can also affect lock time. Typical lock times for random data have a mean of 570us and a max If a specific pattern is repetitive the Deserializer could be misled into a "false lock" - falsely recognizing the data pattern as the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This is when there is more than one Low-High transition in a single clock cycle. This occurs when any bit, except DIN 9, is held at a low state and the adjacent bit is held high creating a 0-1 transition. In the worst case the Deserializer could become locked to the data pattern rather than the clock. Circuitry within the DS92LV1212 can detect that the possibility of "false lock" exists (by detecting that there is more than 1 potential position for clocking bits) and will prevent the LOCK* output from becoming active until the potential "false lock" pattern changes. It is expected that the data will eventually change causing the Deserializer to lose lock to the data pattern and continue searching for the clock bits in the serial data stream. A graphical representation of a few cases of RMT is shown below. Please note that RMT applies to bits DIN0-DIN8.

The Powerdown state is a low power sleep mode that can be used to reduce power when there is no data to be transferred. Powerdown is entered when PWRDN and REN are driven low on the Deserializer. In Powerdown, the PLL is stopped and the outputs go into TRI-STATE, disabling load current and also reducing supply current to the milliamp range. To exit Powerdown, PWRDN is driven high. Both the Serializer and Deserializer must re-initialize and resynchronize before data can be transferred. Initialization of the Serializer takes 1024 TCLK cycles. The Deserializer will initialize and assert LOCK high until it is locked to the Bus LVDS clock.

For the Deserializer, TRI-STATE is entered when the REN pin is driven low. This will TRI-STATE the receiver output pins (ROUT0­ROUT9), LOCK and RCLK.


 

Related products with the same datasheet
DS92LV1212MDC
Some Part number from the same manufacture National Semiconductor Corporation
DS92LV1212A DS92LV1212A - 16 MHZ - 40 MHZ 10-Bit Bus LVDS Random Lock Deserializer With Embedded Clock Recovery, Package: SSOP-EIAJ, Pin Nb=28
DS92LV1212MDC 16 MHZ
DS92LV1212TMSA DS92LV1212 - 16 MHZ - 40 MHZ 10-Bit Bus LVDS Random Lock Deserializer With Embedded Clock Recovery Not Recommended For Designs , Package: SSOP-EIAJ, Pin Nb=28
DS92LV1224 DS92LV1023 - 40 MHz-66MHz 10-Bit Serializer, Package: Evaluation Board, Pin Nb=-
DS92LV1260 DS92LV1260 - Six 1 to 10 Deserializers, Package: Lbga, Pin Nb=196
DS92LV16 DS92LV16 - 16-Bit Bus LVDS Serializer/deserializer - 25 - 80 Mhz, Package: Evaluation Board, Pin Nb=-
DS92LV18 18-Bit Bus LVDS Serializer/deserializer - 15-66 MHZ
DS92LV222A DS92LV222A - Two Channel Bus LVDS Muxed Repeater, Package: Soic Narrow, Pin Nb=16
DS92LV8028 DS92LV8028 - 8 Channel 10:1 Serializer, Package: Lbga, Pin Nb=196
DS92UT16 DS92UT16 - Utopia-lvds Bridge For 1.6 GBPS Bi-directional Data Transfers, Package: Lbga, Pin Nb=196
DS9616HM
DS96172 Rs-485/rs-422 Quad Differential Line Drivers
DS96172CN RS-485/RS-422 Quad Differential Line Drivers
DS96173 DS96173 - RS-485/RS-422 Quad Differential Line Receivers, Package: Mdip, Pin Nb=16
DS96174 DS96174 - RS-485/RS-422 Quad Differential Line Drivers, Package: Mdip, Pin Nb=16
DS96175 DS96173 - RS-485/RS-422 Quad Differential Line Receivers, Package: Mdip, Pin Nb=16
DS96176 DS96176 - RS-485/RS-422 Differential Bus Transceiver, Package: Mdip, Pin Nb=8
DS96177 Rs-485/rs-422 Differential Bus Repeater
DS96177CN RS-485/RS-422 Differential Bus Repeater
DS9622 DS9622 - Dual Line Receiver, Package: Lcc, Pin Nb=20
DS9622ME/883 Dual Line Receiver
Same catergory

54F245FM : Octal Bidirectional Transceiver With Tri-state Outputs. 54F 74F245 Octal Bidirectional Transceiver with TRI-STATE Outputs The 'F245 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications Current sinking capability (20 mA Mil) at the A ports and (48 mA Mil) at the B ports The Transmit Receive (T R) input determines the direction of data flow.

82503 : Dual Serial Transceiver ( DST ). Single Component Ethernet Interface to Both 3 10BASE-T and AUI Automatic or Manual Port Selection Manchester Encoder Decoder and Clock Recovery No Glue Interface to Industry-Standard LAN Controllers Intel 82590 82593 and 82596 AMD 7990 (LANCE ) National Semiconductor 8390 and 83932 (SONIC ) Western Digital 83C690 Fujitsu 86950 (Etherstar ) Diagnostic.

A6B273 : . The A6B273KA and A6B273KLW combine eight (positive-edgetriggered D-type) data latches and DMOS outputs for systems requiring relatively high load power. Driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems.

AC162834ADGG : 18-bit Registered Driver With Inverted Register Enable And 30ohm Termination Resistors 3-state.

HIP0063 : Hex Low Side MOSFET Driver With Serial or Parallel Interface And Diagnostic Fault Control.

LC75842E : General-purpose 1/2 Duty LCD Display Driver. The LC75842E and LC75842M are 1/2 duty generalpurpose LCD display drivers for applications such as microprocessor-controlled electronic tuning. They can drive to 54 segments directly. 1/2 duty, 1/2 bias drive to 54 segments Serial data input supports CCB* format communication with the system controller. Backup function which is based on a power saving.

LC75878W : . The LC75878E and LC75878W are to 1/10 duty general-purpose LCD display drivers used for character and graphics display. These products operate under the control of a microcontroller and can directly drive an LCD with to 730 segments. They can also control to 4 general-purpose output ports. 1/8duty­1/4bias, 1/9duty­1/4bias, and 1/10duty­1/4bias drive.

LSI53C896 : Pci to Dual Channel Ultra2 Scsi Multifunction Controller Technical Manual V3.2 4/01.

LTC1483 : LTC1483, Ultra-low Power Low Emi Transceiver With Shutdown, SO-8. LTC1483 Ultra-Low Power RS485 Low EMI Transceiver with Shutdown Low Power: ICC = 120µA Max with Driver Disabled ICC = 500µA Max with Driver Enabled, No Load 1µA Quiescent Current in Shutdown Mode Controlled Slew Rate Driver for Reduced EMI Single 5V Supply Drivers/Receivers Have ± 10kV ESD Protection to 12V Common-Mode Range Permits ± 7V Ground Difference.

MIC2526 : MIC2526 Dual Usb Power Control Switch. Dual USB Power Control Switch Not Recommended for New Designs The is a dual integrated high-side power switch with independent enable and flag functions, optimized for selfpowered and bus-powered Universal Serial Bus (USB) applications. Few external components are necessary to satisfy USB requirements. The MIC2526 satisfies the following USB requirements:.

SN65HVD232 : . Footprint Bus/Pin ESD Protection Exceeds 16 kV HBM High Input Impedance Allows for 120 Nodes on a Bus Controlled Driver Output Transition Times for Improved Signal Quality on the SN65HVD230 and SN65HVD231 Unpowered Node Does Not Disturb the Bus Compatible With the Requirements of the ISO 11898 Standard Low-Current SN65HVD230 Standby Mode 370 µA Typical.

SN75140 : Dual Line Receiver: 2 Receivers. Single 5-V Supply ±100-mV Sensitivity For Application as: ­ Single-Ended Line Receiver ­ Gated Oscillator ­ Level Comparator Adjustable Reference Voltage TTL Outputs TTL-Compatible Strobe Designed for Party-Line (Data-Bus) Applications Common Reference-Voltage Pin Common Strobe The PS package is only available left-ended taped and reeled (order SN75140.

UR7HCDMP : Mouse encoder. HulaPoint™ - Ergonomic Mouse PS/2 / Serial Encoder.

XRD44L60 : CCD Image Digitizer With Programmable Gain & Power Down. %LW 6DPSOLQJ 5DWH &RUUHODWHG 'RXEOH &'6 3URJUDPPDEOH *DLQ IURP G% 3*$ 'LJLWDO %ODFN /HYHO $XWR&DOLEUDWLRQ &'6 &ORFNV &DQ 6DPSOH 5LVLQJ (GJH RU )DOOLQJ (GJH 3RZHU 6XSSO\ /RZ 3RZHU IRU %DWWHU\ $SSOLFDWLRQV ;5' ;5'/ 'LJLWDO 9LGHR &DPFRUGHUV 'LJLWDO 6WLOO &DPHUDV 9LGHR 7HOHFRQIHUHQFLQJ 'LJLWDO &RSLHUV ,QIUDUHG ,PDJH 'LJLWL]HUV &&'&,6 ,PDJHU ,QWHUIDFH 7KH ;5';5'/.

CY7C68000A : MoBL-USB TX2(TM) USB 2.0 UTMI Transceiver The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB) revision 2.0 transceiver, serial/deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The MoBL-USB TX2 provides a high-speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth.

W83697HG : LPC Interface I/O plus Game/MIDI Port, H/W Monitor, Flash ROM I/F, Pb-free package.

TMDS261 : 2 To 1 HDMI Switch The TMDS261 is a two-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to two DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports.

TSU5611 : SP3T Switch For Micro-USB Applications With USB, UART And Audio Switches And Integrated Impedance The TSU5611 is designed to interface the cellular phone UART, USB, and audio chips with external peripherals via a micro-USB connector. The switch impedance detection for identification of various accessories that are attached through DP and DM of the micro-USB.

 
0-C     D-L     M-R     S-Z