Details, datasheet, quote on part number: DS92LV18
PartDS92LV18
Category
Description18-Bit Bus LVDS Serializer/deserializer - 15-66 MHZ
CompanyNational Semiconductor Corporation
DatasheetDownload DS92LV18 datasheet
Cross ref.Similar parts: DS92LV16TVHG, DS92LV16TVHGX, DS92LV16TVHGX/NOPB
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Features, Applications

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side. The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

Features

n 1566 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps full duplex throughput) n Independent transmitter and receiver operation with separate clock, enable, and power down pins n Hot plug protection (power up high impedance) and synchronization (receiver locks to random data) n Wide 5% reference clock frequency tolerance for easy system design using locally-generated clocks n Line and local loopback modes n Robust BLVDS serial transmission across backplanes and cables for low EMI n No external coding required n Internal PLL, no external PLL components required n Single +3.3V power supply n Low power: 90mA (typ) transmitter, 100mA (typ) at 66 MHz with PRBS-15 pattern 100 mV receiver input threshold n Loss of lock detection and reporting pin n Industrial to +85C temperature range > 2.0kV HBM ESD n Compact, standard 80-pin PQFP package

Maximum Package Power Dissipation Capacity Package Derating: 80L PQFP JA JC ESD Rating (HBM) 23.2 mW/C above 43C/W 11.1C/W

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage LVCMOS/LVTTL Output Voltage Bus LVDS Receiver Input Voltage Bus LVDS Driver Output Voltage Bus LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 seconds) -0.3V to (VCC -0.3V to (VCC to +150C

Min Supply Voltage (VCC) Operating Free Air Temperature (TA) Clock Rate Supply Noise -40 15 Nom 3.3 +25 Max Units V C MHz mV (p-p)

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL Parameter High Level Input Voltage Low Level Input Voltage DEN, TCLK, TPWDN, DIN, ICL -18 mA VIN or 3.6V IOH -9 mA IOL 9 mA VOUT = 0V PWRDN or REN = 0.8V, VOUT 0V or VCC ROUT, RCLK ROUT, RCLK, LOCK SYNC, RCLK_R/F, REN, REFCLK, RPWDN -10 2.3 GND -15 -10 Conditions Pin/Freq. Min 2.0 GND Typ Max VCC 0.8 Units V LVCMOS/LVTTL DC Specifications

Input Clamp Voltage Input Current High Level Output Voltage Low Level Output Voltage Output Short Circuit Current TRI-STATE Output Current

Bus LVDS DC specifications VTH VTL Differential Threshold High Voltage Differential Threshold Low Voltage +100 VCM = +1.1V RI+, RIVIN = +2.4V, VCC or 0V VIN = 0V, VCC -10 mV

Symbol VOD VOS IOS Parameter Output Differential Voltage (DO+) - (DO-) Output Differential Voltage Unbalance Offset Voltage Offset Voltage Unbalance Output Short Circuit Current

(Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Conditions Figure = 100 Pin/Freq. Min 350 Typ = 0V, Din = H, TPWDN and DEN = 2.4V TPWDN or DEN 0V OR VDD = 100 ICCT Total Supply Current (includes load current) = 15 pF, = 100 PWRDN = 0.8V, REN = 66 MHz, PRBS-15 pattern = 66 MHz, Worst case pattern (Checker-board pattern) 1.2 2.7 DO+, DO-35 -50 Max Units mV mA

SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins) 190 mA

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tTCP tTCIH tTCIL tCLKT tJIT Parameter Transmit Clock Period Transmit Clock High Time Transmit Clock Low Time TCLK Input Transition Time TCLK Input Jitter (Note 8) Conditions Min 15.2 0.4T Typ 0.5T 3 Max 6 80 Units ns ps (RMS)

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tLLHT tLHLT tDIS tDIH Parameter Bus LVDS Low-to-High Transition Time Bus LVDS High-to-Low Transition Time DIN (0-17) Setup to TCLK DIN (0-17) Hold from TCLK Conditions Figure 3, (Note CL=10pF to GND Figure 6, (Note CL=10pF to GND 2.4 0 Min Typ 0.2 Max 0.4 Units ns


 

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