Details, datasheet, quote on part number: FLINK3V6BT-65
PartFLINK3V6BT-65
Category
Description
CompanyNational Semiconductor Corporation
DatasheetDownload FLINK3V6BT-65 datasheet
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Features, Applications
DS90C363/DS90CF364 +3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD) Link 65 MHz

DS90C363/DS90CF364 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-- 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-- 65 MHz

The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF364 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec. The Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The Transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge Transmitter will interoperate with a Falling edge Receiver (DS90CF364) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Features

to 65 MHz shift clock support n Programmable Transmitter (DS90C363) strobe select (Rising or Falling edge strobe) n Single 3.3V supply n Chipset (Tx + Rx) power consumption 250 mW (typ) n Power-down mode 0.5 mW total) n Single pixel per clock XGA (1024x768) ready n Supports VGA, SVGA, XGA and higher addressability. to 170 Megabyte/sec bandwidth to 1.3 Gbps throughput n Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 48-lead TSSOP package n Falling edge data strobe Receiver n Compatible with TIA/EIA-644 LVDS standard n ESD rating kV n Operating Temperature: to +85C

Application
TRI-STATE is a registered trademark of National Semiconductor Corporation.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) Maximum Package Power Dissipation MTD48 (TSSOP) Package: to +4V (VCC + 0.3V) (VCC + 0.3V) (VCC + 0.3V) (VCC + 0.3V)

Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min -40 0 Nom 3.3 +25 Max Units C V mVPP

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOS IOS IOZ VTH VTL IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between complimentary output states Offset Voltage (Note 4) Change in V

complimentary output states Output Short Circuit Current Output TRI-STATE Current Differential Input High Threshold Differential Input Low Threshold Input Current -5

TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current, Worst Case = 5 pF, Worst Case Pattern (Figures = 5 pF, 16 Grayscale Pattern (Figures to +85C


 

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