|
|
Part: FPD85308EVK
Category:
Timing Circuits
-> Timers
-> Panel Timing Controller
Description: FPD85308 - Panel Timing Controller, Package: Evaluation Board, Pin Nb=-
Company: National Semiconductor Corporation
Datasheet: Download FPD85308EVK datasheet File size : 3249 kB
Request For quote: Find where to buy FPD85308EVK
Datasheet text preview:
FPD85308 Panel Timing Controller
PRELIMINARY
May 2001
FPD85308 Panel Timing Controller
General Description
The FPD85308 Panel Timing Controller is an integrated FPD-Link based TFT-LCD timing controller. It resides on the flat panel display and provides the interface signal routing and timing control between graphics or video controllers and a TFT-LCD system. FPD-Link is a low power, low electromagnetic interference interface used between this controller and the host system. The FPD85308 chip links the panel's system interface to the LCD display via a ten wire LVDS data bus. The data is then routed to the source and gate display drivers. Both XGA and SVGA resolutions are supported. The FPD85308 is programmable via an optional external serial EEPROM. Reserved space in the EEPROM is available for display identification information. The system can access the EEPROM to read the display identification data or program initialization values used by the FPD85308.
Features
n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n Supports Graphics Controllers with Spread Spectrum interfaces for lower EMI n System programmable via EEPROM n Suitable for notebook and monitor applications n 8-bit or 6-bit system interface n XGA or SVGA capable n Supports single or dual port column drivers n Programmable outputs provide customized control for standard or in-house column drivers and row drivers n Programmable slew rate controlled outputs on CD interface for reduced EMI n Polarity pin reduces CD data bus switching n CMOS circuitry operates from a 3.3V supply
System Diagram
DS101356-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation
DS101356
www.national.com
FPD85308
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Range (TSTG) Lead Temperature (TL) (Soldering 10 sec.) ESD Rating: (CZAP = 120 pF, RZAP = 1500) MM = 200V, HBM = 2000V 4.0V -0.3V to VDD +0.3V -0.3V to VDD +0.3V -65°C to +150°C 260°C
Operating Conditions
Supply Voltage (VDD) Operating Temp. Range (TA) Supply Noise Voltage (VCC) Min 3.0 0 Max 3.6 70 100 Units V °C mVPP
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
DC Electrical Characteristics
Symbol VOH VOL VIH VIL IIN IOZ IDD VTHH VTHL Parameter Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Maximum TRI-STATE Output Leakage Current Average Supply Current Differential Input High Threshold Differential Input Low Threshold
TA = 0°C to 70°C, VDD = 3.3V ± 0.3V (unless otherwise specified) Conditions VDD = 3.0V, IOH = -8 mA VDD = 3.0V, IOL = 8 mA 2.0 0.8 VIN = VDD VIN = VDD, VIN = VSS f = 65 MHz, CLOAD = 50 pF Common Mode Voltage = +1.2V Common Mode Voltage = +1.2V -100 10 10 312 +100 Min 2.4 0.4 Max Units V V V V µA µA mA mV mV
Device Specifications
Symbol RPLLS RCCS
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) Conditions Min Max 10 700 Units ms ps
Parameter Receiver Phase Lock Loop Set Time RxIN Channel-to-Channel Skew (Note 2)
Note 2: This limit assumes a maximum cable skew of 350 ps. Actual automated test equipment limit is 400 ps due to tester accuracy.
DS101356-12
FIGURE 1. FPD85308 (Receiver) Phase Lock Loop Set Time
www.national.com
2
FPD85308
Device Specifications
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) (Continued)
DS101356-26
FIGURE 2. FPD85308 Power-up Sequencing
DS101356-13
Note 3: Measurements at VDIFF = 0V Note 4: RCCS measured between earliest and latest LVDS edges Note 5: *RxIN3 pair (RxIN_3 ± ) is option for 24-bit color depth
FIGURE 3. FPD85308 (Receiver) Channel-to-Channel Skew and Pulse Width
3
www.national.com
FPD85308
Device Specifications
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) (Continued)
DS101356-27
Note:
R/G/B[5] are MSBs and R/G/B[0] are LSBs
FIGURE 4. FPD85308-6 bit Input Mapping
DS101356-28
Note:
R/G/B[7] are MSBs and R/G/B[0] are LSBs
FIGURE 5. FPD85308-8 bit Input Mapping Symbol SPsetup SPhold RGBsetup RGBhold CLKpw CLKperiod Parameter E/OSP from E/OCLK E/OSP from E/OCLK ER/EG/EB/OR/OG/OB from E/OCLK ER/EG/EB/OR/OG/OB from E/OCLK E/OCLK pulsewidth E/OCLK period Conditions 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) Min 8 8 8 8 11 30 Max Units ns ns ns ns ns ns
Note 6: Timing applies to Dual Bus output modes.
www.national.com
4
FPD85308
Device Specifications
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) (Continued)
DS101356-15
FIGURE 6. Column Driver Bus AC Timing
DS101356-16
FIGURE 7. Vertical Backporch Definition (Video Data from Host)
DS101356-17
FIGURE 8. Horizontal Backporch Definition (Video Data from Host)
5
www.national.com
Others parts begin by fp
FP-1 FP-2 FP-3
|
|
|
