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Details, datasheet, quote on part number:FPD85310VJD
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Datasheet text preview:
FPD85310 Panel Timing Controller
September 1999
FPD85310 Panel Timing Controller
General Description
The FPD85310 Panel Timing Controller is an integrated FPD-Link based TFT-LCD timing controller. It resides on the flat panel display and provides the interface signal routing and timing control between graphics or video controllers and a TFT-LCD system. FPD-Link is a low power, low electromagnetic interference interface used between this controller and the host system. The FPD85310 chip links the panel's system interface to the display via a ten wire LVDS data bus. That data is then routed to the source and gate display drivers. XGA and SVGA resolutions are supported. The FPD85310 is programmable via an optional external serial EEPROM. Reserved space in the EEPROM is available for display identification information. The system can access the EEPROM to read the display identification data or program initialization values used by the FPD85310.
Features
n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n System programmable via EEPROM n Suitable for notebook and monitor applications n 8-bit or 6-bit system interface n XGA or SVGA capable n Supports single or dual port column drivers n Programmable outputs provide customized control for standard or in-house column drivers and row drivers n Fail-safe operation prevents panel damage with system clock failure n Programmable skew rate controlled outputs on CD interface for reduced EMI n Polarity pin reduces CD data bus switching n CMOS circuitry operates from a 3.3V supply
System Diagram
DS101086-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS101086
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Range (TSTG) Lead Temperature (TL) (Soldering 10 sec.) -0.5V to VDD -0.5V to VDD 4.1V +0.5V +0.5V
ESD Rating: (CZAP = 120 pF, RZAP = 1500) MM = 200V, HBM = 2000V
Operating Conditions
Supply Voltage (VDD) Operating Temp. Range (TA) Min 3.0 0 Max 3.6 70 Units V °C
-65°C to +150°C 260°C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
DC Electrical Characteristics
Symbol VOH VOL VIH VIL IIN IOZ IDD VTHH VTHL Parameter Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Maximum TRI-STATE Output Leakage Current Average Supply Current Differential Input High Threshold Differential Input Low Threshold
TA = 0°C to 70°C, VDD = 3.3V ± 0.3V (unless otherwise specified) Conditions VDD = 3.0V, IOH = 1 mA VDD = 3.0V, IOL = 1 mA 2.0 0.8 VIN = VDD VIN = VDD, VIN = VSS f = 65 MHz, CLOAD = 50 pF Common Mode Voltage = +1.2V Common Mode Voltage = +1.2V -100 10 10 312 +100 Min 2.4 0.4 Max Units V V V V µA µA mA mV mV
Device Specifications
Symbol RPLLS RCCS
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) Conditions Min Max 10 700 Units ms ps
Parameter Receiver Phase Lock Loop Set Time RxIN Channel-to-Channel Skew (Note 2)
Note 2: This limit assumes a maximum cable skew of 350 ps. Actual automated test equipment limit is 400 ps due to tester accuracy.
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FIGURE 1. FPD85310 (Receiver) Phase Lock Loop Set Time
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Device Specifications
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) (Continued)
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Note 3: Measurements at VDIFF = 0V Note 4: RCCS measured between earliest and latest LVDS edges Note 5: *RxIN3 pair (RxIN_3 ± ) is option for 24-bit color depth
FIGURE 2. FPD85310 (Receiver) Channel-to-Channel Skew and Pulse Width
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FIGURE 3. FPD85310's (Receiver) Format of the Input Data Symbol SPsetup SPhold RGBsetup RGBhold CLKpw CLKperiod Parameter E/OSP from E/OCLK E/OSP from E/OCLK ER/EG/EB/OR/OG/OB from E/OCLK ER/EG/EB/OR/OG/OB from E/OCLK E/OCLK pulsewidth E/OCLK period Conditions 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) 65 MHz Video (Note 6) Min 8 8 8 8 11 25 Max Units ns ns ns ns ns ns
Note 6: Timing applies to Dual Bus output modes.
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FIGURE 4. Column Driver Bus AC Timing
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Device Specifications
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) (Continued)
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FIGURE 5. Vertical Backporch Definition (Video Data from Host)
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FIGURE 6. Horizontal Backporch Definition (Video Data from Host)
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Internal Pixel Count final value = pixels per line/2 Maximum Internal Pixel Count = 1024 (32.5 MHz clocks) Internal Pixel Count is used to generate the horizontal_component for GPO generation See Figure 9 **Without Blanking control (GPO8), random data may be observed during 16 OCLK and discontinuous 1 OCLK before E/OSP, but it should not be affected to actual image.
FIGURE 7. Internal Pixel Count Used for GPO Control Generation
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Device Specifications
TA = 0°C to 70°C, VDD = 3.3V (unless otherwise specified) (Continued)
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LC = lines per frame count, LCmax = 2048 lines Internal Line Count is used to generate the vertical component for GPO generation See Figure 9
FIGURE 8. Internal Line Count Used for GPO Control Generation GPO Generation
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GPO Combination Select
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FIGURE 9. GPO Control Generation
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